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<div class="header">
  <div class="headertitle"><div class="title">stm32h7xx_ll_dma.h</div></div>
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<a href="stm32h7xx__ll__dma_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span></div>
<div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span> </div>
<div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">/* Define to prevent recursive inclusion -------------------------------------*/</span></div>
<div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="preprocessor">#ifndef STM32H7xx_LL_DMA_H</span></div>
<div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="preprocessor">#define STM32H7xx_LL_DMA_H</span></div>
<div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span> </div>
<div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div>
<div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span><span class="preprocessor">#endif</span></div>
<div class="line"><a id="l00026" name="l00026"></a><span class="lineno">   26</span> </div>
<div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span><span class="comment">/* Includes ------------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span><span class="preprocessor">#include &quot;<a class="code" href="stm32h7xx_8h.html">stm32h7xx.h</a>&quot;</span></div>
<div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span><span class="preprocessor">#include &quot;<a class="code" href="stm32h7xx__ll__dmamux_8h.html">stm32h7xx_ll_dmamux.h</a>&quot;</span></div>
<div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span></div>
<div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span> </div>
<div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span><span class="preprocessor">#if defined (DMA1) || defined (DMA2)</span></div>
<div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span></div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span> </div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span><span class="comment">/* Private types -------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span><span class="comment">/* Private variables ---------------------------------------------------------*/</span></div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span><span class="comment">/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */</span></div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span><span class="keyword">static</span> <span class="keyword">const</span> uint8_t LL_DMA_STR_OFFSET_TAB[] =</div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>{</div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),</div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),</div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),</div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),</div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),</div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),</div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),</div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)</div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>};</div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span> </div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span></div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span> </div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span><span class="comment">/* Private macros ------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span><span class="preprocessor">#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \</span></div>
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span><span class="preprocessor">(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span> </div>
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span><span class="comment">/* Exported types ------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span><span class="preprocessor">#if defined(USE_FULL_LL_DRIVER)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>{</div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>  uint32_t PeriphOrM2MSrcAddress;       </div>
<div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span> </div>
<div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>  uint32_t MemoryOrM2MDstAddress;       </div>
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span> </div>
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>  uint32_t Direction;                   </div>
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span> </div>
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>  uint32_t Mode;                        </div>
<div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span> </div>
<div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>  uint32_t PeriphOrM2MSrcIncMode;       </div>
<div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span> </div>
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>  uint32_t MemoryOrM2MDstIncMode;       </div>
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span> </div>
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span>  uint32_t PeriphOrM2MSrcDataSize;      </div>
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span> </div>
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span>  uint32_t MemoryOrM2MDstDataSize;      </div>
<div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span> </div>
<div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>  uint32_t NbData;                      </div>
<div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span> </div>
<div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>  uint32_t PeriphRequest;               </div>
<div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span> </div>
<div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span>  uint32_t Priority;                    </div>
<div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span> </div>
<div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>  uint32_t FIFOMode;                    </div>
<div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span> </div>
<div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span>  uint32_t FIFOThreshold;               </div>
<div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span> </div>
<div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>  uint32_t MemBurst;                    </div>
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span> </div>
<div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>  uint32_t PeriphBurst;                 </div>
<div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span> </div>
<div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>  uint32_t DoubleBufferMode;            </div>
<div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span> </div>
<div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span>  uint32_t TargetMemInDoubleBufferMode; </div>
<div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span>} LL_DMA_InitTypeDef;</div>
<div class="line"><a id="l00193" name="l00193"></a><span class="lineno">  193</span><span class="preprocessor">#endif </span><span class="comment">/*USE_FULL_LL_DRIVER*/</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span><span class="comment">/* Exported constants --------------------------------------------------------*/</span></div>
<div class="line"><a id="l00198" name="l00198"></a><span class="lineno">  198</span></div>
<div class="line"><a id="l00202" name="l00202"></a><span class="lineno">  202</span><span class="preprocessor">#define LL_DMA_STREAM_0                   0x00000000U</span></div>
<div class="line"><a id="l00203" name="l00203"></a><span class="lineno">  203</span><span class="preprocessor">#define LL_DMA_STREAM_1                   0x00000001U</span></div>
<div class="line"><a id="l00204" name="l00204"></a><span class="lineno">  204</span><span class="preprocessor">#define LL_DMA_STREAM_2                   0x00000002U</span></div>
<div class="line"><a id="l00205" name="l00205"></a><span class="lineno">  205</span><span class="preprocessor">#define LL_DMA_STREAM_3                   0x00000003U</span></div>
<div class="line"><a id="l00206" name="l00206"></a><span class="lineno">  206</span><span class="preprocessor">#define LL_DMA_STREAM_4                   0x00000004U</span></div>
<div class="line"><a id="l00207" name="l00207"></a><span class="lineno">  207</span><span class="preprocessor">#define LL_DMA_STREAM_5                   0x00000005U</span></div>
<div class="line"><a id="l00208" name="l00208"></a><span class="lineno">  208</span><span class="preprocessor">#define LL_DMA_STREAM_6                   0x00000006U</span></div>
<div class="line"><a id="l00209" name="l00209"></a><span class="lineno">  209</span><span class="preprocessor">#define LL_DMA_STREAM_7                   0x00000007U</span></div>
<div class="line"><a id="l00210" name="l00210"></a><span class="lineno">  210</span><span class="preprocessor">#define LL_DMA_STREAM_ALL                 0xFFFF0000U</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00214" name="l00214"></a><span class="lineno">  214</span> </div>
<div class="line"><a id="l00215" name="l00215"></a><span class="lineno">  215</span></div>
<div class="line"><a id="l00219" name="l00219"></a><span class="lineno">  219</span><span class="preprocessor">#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00220" name="l00220"></a><span class="lineno">  220</span><span class="preprocessor">#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00221" name="l00221"></a><span class="lineno">  221</span><span class="preprocessor">#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00225" name="l00225"></a><span class="lineno">  225</span></div>
<div class="line"><a id="l00229" name="l00229"></a><span class="lineno">  229</span><span class="preprocessor">#define LL_DMA_MODE_NORMAL                0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00230" name="l00230"></a><span class="lineno">  230</span><span class="preprocessor">#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00231" name="l00231"></a><span class="lineno">  231</span><span class="preprocessor">#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00235" name="l00235"></a><span class="lineno">  235</span></div>
<div class="line"><a id="l00239" name="l00239"></a><span class="lineno">  239</span><span class="preprocessor">#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00240" name="l00240"></a><span class="lineno">  240</span><span class="preprocessor">#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00244" name="l00244"></a><span class="lineno">  244</span></div>
<div class="line"><a id="l00248" name="l00248"></a><span class="lineno">  248</span><span class="preprocessor">#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00249" name="l00249"></a><span class="lineno">  249</span><span class="preprocessor">#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00253" name="l00253"></a><span class="lineno">  253</span></div>
<div class="line"><a id="l00257" name="l00257"></a><span class="lineno">  257</span><span class="preprocessor">#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00258" name="l00258"></a><span class="lineno">  258</span><span class="preprocessor">#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00262" name="l00262"></a><span class="lineno">  262</span></div>
<div class="line"><a id="l00266" name="l00266"></a><span class="lineno">  266</span><span class="preprocessor">#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00267" name="l00267"></a><span class="lineno">  267</span><span class="preprocessor">#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00271" name="l00271"></a><span class="lineno">  271</span></div>
<div class="line"><a id="l00275" name="l00275"></a><span class="lineno">  275</span><span class="preprocessor">#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00276" name="l00276"></a><span class="lineno">  276</span><span class="preprocessor">#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00277" name="l00277"></a><span class="lineno">  277</span><span class="preprocessor">#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00281" name="l00281"></a><span class="lineno">  281</span></div>
<div class="line"><a id="l00285" name="l00285"></a><span class="lineno">  285</span><span class="preprocessor">#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00286" name="l00286"></a><span class="lineno">  286</span><span class="preprocessor">#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00287" name="l00287"></a><span class="lineno">  287</span><span class="preprocessor">#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00291" name="l00291"></a><span class="lineno">  291</span></div>
<div class="line"><a id="l00295" name="l00295"></a><span class="lineno">  295</span><span class="preprocessor">#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00296" name="l00296"></a><span class="lineno">  296</span><span class="preprocessor">#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00300" name="l00300"></a><span class="lineno">  300</span></div>
<div class="line"><a id="l00304" name="l00304"></a><span class="lineno">  304</span><span class="preprocessor">#define LL_DMA_PRIORITY_LOW               0x00000000U               </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00305" name="l00305"></a><span class="lineno">  305</span><span class="preprocessor">#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00306" name="l00306"></a><span class="lineno">  306</span><span class="preprocessor">#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00307" name="l00307"></a><span class="lineno">  307</span><span class="preprocessor">#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00311" name="l00311"></a><span class="lineno">  311</span> </div>
<div class="line"><a id="l00312" name="l00312"></a><span class="lineno">  312</span></div>
<div class="line"><a id="l00316" name="l00316"></a><span class="lineno">  316</span><span class="preprocessor">#define LL_DMA_MBURST_SINGLE              0x00000000U                             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00317" name="l00317"></a><span class="lineno">  317</span><span class="preprocessor">#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00318" name="l00318"></a><span class="lineno">  318</span><span class="preprocessor">#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00319" name="l00319"></a><span class="lineno">  319</span><span class="preprocessor">#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00323" name="l00323"></a><span class="lineno">  323</span></div>
<div class="line"><a id="l00327" name="l00327"></a><span class="lineno">  327</span><span class="preprocessor">#define LL_DMA_PBURST_SINGLE              0x00000000U                             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00328" name="l00328"></a><span class="lineno">  328</span><span class="preprocessor">#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00329" name="l00329"></a><span class="lineno">  329</span><span class="preprocessor">#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00330" name="l00330"></a><span class="lineno">  330</span><span class="preprocessor">#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00334" name="l00334"></a><span class="lineno">  334</span></div>
<div class="line"><a id="l00338" name="l00338"></a><span class="lineno">  338</span><span class="preprocessor">#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00339" name="l00339"></a><span class="lineno">  339</span><span class="preprocessor">#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00343" name="l00343"></a><span class="lineno">  343</span></div>
<div class="line"><a id="l00347" name="l00347"></a><span class="lineno">  347</span><span class="preprocessor">#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00348" name="l00348"></a><span class="lineno">  348</span><span class="preprocessor">#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00349" name="l00349"></a><span class="lineno">  349</span><span class="preprocessor">#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00350" name="l00350"></a><span class="lineno">  350</span><span class="preprocessor">#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00351" name="l00351"></a><span class="lineno">  351</span><span class="preprocessor">#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00352" name="l00352"></a><span class="lineno">  352</span><span class="preprocessor">#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00356" name="l00356"></a><span class="lineno">  356</span></div>
<div class="line"><a id="l00360" name="l00360"></a><span class="lineno">  360</span><span class="preprocessor">#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00361" name="l00361"></a><span class="lineno">  361</span><span class="preprocessor">#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00362" name="l00362"></a><span class="lineno">  362</span><span class="preprocessor">#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         </span><span class="preprocessor"></span></div>
<div class="line"><a id="l00363" name="l00363"></a><span class="lineno">  363</span><span class="preprocessor">#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           </span><span class="preprocessor"></span><span class="preprocessor"></span></div>
<div class="line"><a id="l00367" name="l00367"></a><span class="lineno">  367</span></div>
<div class="line"><a id="l00371" name="l00371"></a><span class="lineno">  371</span> </div>
<div class="line"><a id="l00372" name="l00372"></a><span class="lineno">  372</span><span class="comment">/* Exported macro ------------------------------------------------------------*/</span></div>
<div class="line"><a id="l00376" name="l00376"></a><span class="lineno">  376</span></div>
<div class="line"><a id="l00387" name="l00387"></a><span class="lineno">  387</span><span class="preprocessor">#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)-&gt;__REG__, (__VALUE__))</span></div>
<div class="line"><a id="l00388" name="l00388"></a><span class="lineno">  388</span></div>
<div class="line"><a id="l00395" name="l00395"></a><span class="lineno">  395</span><span class="preprocessor">#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__-&gt;__REG__)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l00399" name="l00399"></a><span class="lineno">  399</span></div>
<div class="line"><a id="l00408" name="l00408"></a><span class="lineno">  408</span><span class="preprocessor">#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \</span></div>
<div class="line"><a id="l00409" name="l00409"></a><span class="lineno">  409</span><span class="preprocessor">(((uint32_t)(__STREAM_INSTANCE__) &gt; ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)</span></div>
<div class="line"><a id="l00410" name="l00410"></a><span class="lineno">  410</span></div>
<div class="line"><a id="l00416" name="l00416"></a><span class="lineno">  416</span><span class="preprocessor">#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \</span></div>
<div class="line"><a id="l00417" name="l00417"></a><span class="lineno">  417</span><span class="preprocessor">(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \</span></div>
<div class="line"><a id="l00418" name="l00418"></a><span class="lineno">  418</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \</span></div>
<div class="line"><a id="l00419" name="l00419"></a><span class="lineno">  419</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \</span></div>
<div class="line"><a id="l00420" name="l00420"></a><span class="lineno">  420</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \</span></div>
<div class="line"><a id="l00421" name="l00421"></a><span class="lineno">  421</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \</span></div>
<div class="line"><a id="l00422" name="l00422"></a><span class="lineno">  422</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \</span></div>
<div class="line"><a id="l00423" name="l00423"></a><span class="lineno">  423</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \</span></div>
<div class="line"><a id="l00424" name="l00424"></a><span class="lineno">  424</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \</span></div>
<div class="line"><a id="l00425" name="l00425"></a><span class="lineno">  425</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \</span></div>
<div class="line"><a id="l00426" name="l00426"></a><span class="lineno">  426</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \</span></div>
<div class="line"><a id="l00427" name="l00427"></a><span class="lineno">  427</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \</span></div>
<div class="line"><a id="l00428" name="l00428"></a><span class="lineno">  428</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \</span></div>
<div class="line"><a id="l00429" name="l00429"></a><span class="lineno">  429</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \</span></div>
<div class="line"><a id="l00430" name="l00430"></a><span class="lineno">  430</span><span class="preprocessor"> ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \</span></div>
<div class="line"><a id="l00431" name="l00431"></a><span class="lineno">  431</span><span class="preprocessor"> LL_DMA_STREAM_7)</span></div>
<div class="line"><a id="l00432" name="l00432"></a><span class="lineno">  432</span></div>
<div class="line"><a id="l00439" name="l00439"></a><span class="lineno">  439</span><span class="preprocessor">#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \</span></div>
<div class="line"><a id="l00440" name="l00440"></a><span class="lineno">  440</span><span class="preprocessor">((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \</span></div>
<div class="line"><a id="l00441" name="l00441"></a><span class="lineno">  441</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \</span></div>
<div class="line"><a id="l00442" name="l00442"></a><span class="lineno">  442</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \</span></div>
<div class="line"><a id="l00443" name="l00443"></a><span class="lineno">  443</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \</span></div>
<div class="line"><a id="l00444" name="l00444"></a><span class="lineno">  444</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \</span></div>
<div class="line"><a id="l00445" name="l00445"></a><span class="lineno">  445</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \</span></div>
<div class="line"><a id="l00446" name="l00446"></a><span class="lineno">  446</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \</span></div>
<div class="line"><a id="l00447" name="l00447"></a><span class="lineno">  447</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \</span></div>
<div class="line"><a id="l00448" name="l00448"></a><span class="lineno">  448</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \</span></div>
<div class="line"><a id="l00449" name="l00449"></a><span class="lineno">  449</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \</span></div>
<div class="line"><a id="l00450" name="l00450"></a><span class="lineno">  450</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \</span></div>
<div class="line"><a id="l00451" name="l00451"></a><span class="lineno">  451</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \</span></div>
<div class="line"><a id="l00452" name="l00452"></a><span class="lineno">  452</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \</span></div>
<div class="line"><a id="l00453" name="l00453"></a><span class="lineno">  453</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \</span></div>
<div class="line"><a id="l00454" name="l00454"></a><span class="lineno">  454</span><span class="preprocessor"> (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) &amp;&amp; ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \</span></div>
<div class="line"><a id="l00455" name="l00455"></a><span class="lineno">  455</span><span class="preprocessor"> DMA2_Stream7)</span></div>
<div class="line"><a id="l00456" name="l00456"></a><span class="lineno">  456</span></div>
<div class="line"><a id="l00460" name="l00460"></a><span class="lineno">  460</span></div>
<div class="line"><a id="l00464" name="l00464"></a><span class="lineno">  464</span> </div>
<div class="line"><a id="l00465" name="l00465"></a><span class="lineno">  465</span> </div>
<div class="line"><a id="l00466" name="l00466"></a><span class="lineno">  466</span><span class="comment">/* Exported functions --------------------------------------------------------*/</span></div>
<div class="line"><a id="l00470" name="l00470"></a><span class="lineno">  470</span></div>
<div class="line"><a id="l00489" name="l00489"></a><span class="lineno">  489</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableStream(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00490" name="l00490"></a><span class="lineno">  490</span>{</div>
<div class="line"><a id="l00491" name="l00491"></a><span class="lineno">  491</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00492" name="l00492"></a><span class="lineno">  492</span> </div>
<div class="line"><a id="l00493" name="l00493"></a><span class="lineno">  493</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e">DMA_SxCR_EN</a>);</div>
<div class="line"><a id="l00494" name="l00494"></a><span class="lineno">  494</span>}</div>
<div class="line"><a id="l00495" name="l00495"></a><span class="lineno">  495</span></div>
<div class="line"><a id="l00511" name="l00511"></a><span class="lineno">  511</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableStream(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00512" name="l00512"></a><span class="lineno">  512</span>{</div>
<div class="line"><a id="l00513" name="l00513"></a><span class="lineno">  513</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00514" name="l00514"></a><span class="lineno">  514</span> </div>
<div class="line"><a id="l00515" name="l00515"></a><span class="lineno">  515</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e">DMA_SxCR_EN</a>);</div>
<div class="line"><a id="l00516" name="l00516"></a><span class="lineno">  516</span>}</div>
<div class="line"><a id="l00517" name="l00517"></a><span class="lineno">  517</span></div>
<div class="line"><a id="l00533" name="l00533"></a><span class="lineno">  533</span>__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00534" name="l00534"></a><span class="lineno">  534</span>{</div>
<div class="line"><a id="l00535" name="l00535"></a><span class="lineno">  535</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00536" name="l00536"></a><span class="lineno">  536</span> </div>
<div class="line"><a id="l00537" name="l00537"></a><span class="lineno">  537</span>  <span class="keywordflow">return</span> ((READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e">DMA_SxCR_EN</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e">DMA_SxCR_EN</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l00538" name="l00538"></a><span class="lineno">  538</span>}</div>
<div class="line"><a id="l00539" name="l00539"></a><span class="lineno">  539</span></div>
<div class="line"><a id="l00574" name="l00574"></a><span class="lineno">  574</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ConfigTransfer(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t Configuration)</div>
<div class="line"><a id="l00575" name="l00575"></a><span class="lineno">  575</span>{</div>
<div class="line"><a id="l00576" name="l00576"></a><span class="lineno">  576</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00577" name="l00577"></a><span class="lineno">  577</span> </div>
<div class="line"><a id="l00578" name="l00578"></a><span class="lineno">  578</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR,</div>
<div class="line"><a id="l00579" name="l00579"></a><span class="lineno">  579</span>             <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga16bc78076551c42cbdc084e9d0006bd4">DMA_SxCR_DIR</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadc248dbc519cc580621cdadcdd8741fb">DMA_SxCR_CIRC</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga29c5d5c559dd14646fdc170e74f1f03b">DMA_SxCR_PINC</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga771a295832a584a3777ede523a691719">DMA_SxCR_MINC</a> | DMA_SxCR_PSIZE | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae9a98cb706a722d726d8ec6e9fe4a773">DMA_SxCR_MSIZE</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga14c115d71a4e3b3c4da360108288154c">DMA_SxCR_PL</a> | \</div>
<div class="line"><a id="l00580" name="l00580"></a><span class="lineno">  580</span>             <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga11f412d256043bec3e01ceef7f2099f2">DMA_SxCR_PFCTRL</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497">DMA_SxCR_DBM</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadd36c677ee53f56dc408cd549e64cf7d">DMA_SxCR_CT</a>, Configuration);</div>
<div class="line"><a id="l00581" name="l00581"></a><span class="lineno">  581</span>}</div>
<div class="line"><a id="l00582" name="l00582"></a><span class="lineno">  582</span></div>
<div class="line"><a id="l00602" name="l00602"></a><span class="lineno">  602</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetDataTransferDirection(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t  Direction)</div>
<div class="line"><a id="l00603" name="l00603"></a><span class="lineno">  603</span>{</div>
<div class="line"><a id="l00604" name="l00604"></a><span class="lineno">  604</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00605" name="l00605"></a><span class="lineno">  605</span> </div>
<div class="line"><a id="l00606" name="l00606"></a><span class="lineno">  606</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga16bc78076551c42cbdc084e9d0006bd4">DMA_SxCR_DIR</a>, Direction);</div>
<div class="line"><a id="l00607" name="l00607"></a><span class="lineno">  607</span>}</div>
<div class="line"><a id="l00608" name="l00608"></a><span class="lineno">  608</span></div>
<div class="line"><a id="l00627" name="l00627"></a><span class="lineno">  627</span>__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00628" name="l00628"></a><span class="lineno">  628</span>{</div>
<div class="line"><a id="l00629" name="l00629"></a><span class="lineno">  629</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00630" name="l00630"></a><span class="lineno">  630</span> </div>
<div class="line"><a id="l00631" name="l00631"></a><span class="lineno">  631</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga16bc78076551c42cbdc084e9d0006bd4">DMA_SxCR_DIR</a>));</div>
<div class="line"><a id="l00632" name="l00632"></a><span class="lineno">  632</span>}</div>
<div class="line"><a id="l00633" name="l00633"></a><span class="lineno">  633</span></div>
<div class="line"><a id="l00654" name="l00654"></a><span class="lineno">  654</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t Mode)</div>
<div class="line"><a id="l00655" name="l00655"></a><span class="lineno">  655</span>{</div>
<div class="line"><a id="l00656" name="l00656"></a><span class="lineno">  656</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00657" name="l00657"></a><span class="lineno">  657</span> </div>
<div class="line"><a id="l00658" name="l00658"></a><span class="lineno">  658</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadc248dbc519cc580621cdadcdd8741fb">DMA_SxCR_CIRC</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga11f412d256043bec3e01ceef7f2099f2">DMA_SxCR_PFCTRL</a>, Mode);</div>
<div class="line"><a id="l00659" name="l00659"></a><span class="lineno">  659</span>}</div>
<div class="line"><a id="l00660" name="l00660"></a><span class="lineno">  660</span></div>
<div class="line"><a id="l00680" name="l00680"></a><span class="lineno">  680</span>__STATIC_INLINE uint32_t LL_DMA_GetMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00681" name="l00681"></a><span class="lineno">  681</span>{</div>
<div class="line"><a id="l00682" name="l00682"></a><span class="lineno">  682</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00683" name="l00683"></a><span class="lineno">  683</span> </div>
<div class="line"><a id="l00684" name="l00684"></a><span class="lineno">  684</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadc248dbc519cc580621cdadcdd8741fb">DMA_SxCR_CIRC</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga11f412d256043bec3e01ceef7f2099f2">DMA_SxCR_PFCTRL</a>));</div>
<div class="line"><a id="l00685" name="l00685"></a><span class="lineno">  685</span>}</div>
<div class="line"><a id="l00686" name="l00686"></a><span class="lineno">  686</span></div>
<div class="line"><a id="l00705" name="l00705"></a><span class="lineno">  705</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetPeriphIncMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t IncrementMode)</div>
<div class="line"><a id="l00706" name="l00706"></a><span class="lineno">  706</span>{</div>
<div class="line"><a id="l00707" name="l00707"></a><span class="lineno">  707</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00708" name="l00708"></a><span class="lineno">  708</span> </div>
<div class="line"><a id="l00709" name="l00709"></a><span class="lineno">  709</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga29c5d5c559dd14646fdc170e74f1f03b">DMA_SxCR_PINC</a>, IncrementMode);</div>
<div class="line"><a id="l00710" name="l00710"></a><span class="lineno">  710</span>}</div>
<div class="line"><a id="l00711" name="l00711"></a><span class="lineno">  711</span></div>
<div class="line"><a id="l00729" name="l00729"></a><span class="lineno">  729</span>__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00730" name="l00730"></a><span class="lineno">  730</span>{</div>
<div class="line"><a id="l00731" name="l00731"></a><span class="lineno">  731</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00732" name="l00732"></a><span class="lineno">  732</span> </div>
<div class="line"><a id="l00733" name="l00733"></a><span class="lineno">  733</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga29c5d5c559dd14646fdc170e74f1f03b">DMA_SxCR_PINC</a>));</div>
<div class="line"><a id="l00734" name="l00734"></a><span class="lineno">  734</span>}</div>
<div class="line"><a id="l00735" name="l00735"></a><span class="lineno">  735</span></div>
<div class="line"><a id="l00754" name="l00754"></a><span class="lineno">  754</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetMemoryIncMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t IncrementMode)</div>
<div class="line"><a id="l00755" name="l00755"></a><span class="lineno">  755</span>{</div>
<div class="line"><a id="l00756" name="l00756"></a><span class="lineno">  756</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00757" name="l00757"></a><span class="lineno">  757</span> </div>
<div class="line"><a id="l00758" name="l00758"></a><span class="lineno">  758</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga771a295832a584a3777ede523a691719">DMA_SxCR_MINC</a>, IncrementMode);</div>
<div class="line"><a id="l00759" name="l00759"></a><span class="lineno">  759</span>}</div>
<div class="line"><a id="l00760" name="l00760"></a><span class="lineno">  760</span></div>
<div class="line"><a id="l00778" name="l00778"></a><span class="lineno">  778</span>__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00779" name="l00779"></a><span class="lineno">  779</span>{</div>
<div class="line"><a id="l00780" name="l00780"></a><span class="lineno">  780</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00781" name="l00781"></a><span class="lineno">  781</span> </div>
<div class="line"><a id="l00782" name="l00782"></a><span class="lineno">  782</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga771a295832a584a3777ede523a691719">DMA_SxCR_MINC</a>));</div>
<div class="line"><a id="l00783" name="l00783"></a><span class="lineno">  783</span>}</div>
<div class="line"><a id="l00784" name="l00784"></a><span class="lineno">  784</span></div>
<div class="line"><a id="l00804" name="l00804"></a><span class="lineno">  804</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetPeriphSize(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t  Size)</div>
<div class="line"><a id="l00805" name="l00805"></a><span class="lineno">  805</span>{</div>
<div class="line"><a id="l00806" name="l00806"></a><span class="lineno">  806</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00807" name="l00807"></a><span class="lineno">  807</span> </div>
<div class="line"><a id="l00808" name="l00808"></a><span class="lineno">  808</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, DMA_SxCR_PSIZE, Size);</div>
<div class="line"><a id="l00809" name="l00809"></a><span class="lineno">  809</span>}</div>
<div class="line"><a id="l00810" name="l00810"></a><span class="lineno">  810</span></div>
<div class="line"><a id="l00829" name="l00829"></a><span class="lineno">  829</span>__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00830" name="l00830"></a><span class="lineno">  830</span>{</div>
<div class="line"><a id="l00831" name="l00831"></a><span class="lineno">  831</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00832" name="l00832"></a><span class="lineno">  832</span> </div>
<div class="line"><a id="l00833" name="l00833"></a><span class="lineno">  833</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, DMA_SxCR_PSIZE));</div>
<div class="line"><a id="l00834" name="l00834"></a><span class="lineno">  834</span>}</div>
<div class="line"><a id="l00835" name="l00835"></a><span class="lineno">  835</span></div>
<div class="line"><a id="l00855" name="l00855"></a><span class="lineno">  855</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetMemorySize(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t  Size)</div>
<div class="line"><a id="l00856" name="l00856"></a><span class="lineno">  856</span>{</div>
<div class="line"><a id="l00857" name="l00857"></a><span class="lineno">  857</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00858" name="l00858"></a><span class="lineno">  858</span> </div>
<div class="line"><a id="l00859" name="l00859"></a><span class="lineno">  859</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae9a98cb706a722d726d8ec6e9fe4a773">DMA_SxCR_MSIZE</a>, Size);</div>
<div class="line"><a id="l00860" name="l00860"></a><span class="lineno">  860</span>}</div>
<div class="line"><a id="l00861" name="l00861"></a><span class="lineno">  861</span></div>
<div class="line"><a id="l00880" name="l00880"></a><span class="lineno">  880</span>__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00881" name="l00881"></a><span class="lineno">  881</span>{</div>
<div class="line"><a id="l00882" name="l00882"></a><span class="lineno">  882</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00883" name="l00883"></a><span class="lineno">  883</span> </div>
<div class="line"><a id="l00884" name="l00884"></a><span class="lineno">  884</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae9a98cb706a722d726d8ec6e9fe4a773">DMA_SxCR_MSIZE</a>));</div>
<div class="line"><a id="l00885" name="l00885"></a><span class="lineno">  885</span>}</div>
<div class="line"><a id="l00886" name="l00886"></a><span class="lineno">  886</span></div>
<div class="line"><a id="l00905" name="l00905"></a><span class="lineno">  905</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetIncOffsetSize(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t OffsetSize)</div>
<div class="line"><a id="l00906" name="l00906"></a><span class="lineno">  906</span>{</div>
<div class="line"><a id="l00907" name="l00907"></a><span class="lineno">  907</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00908" name="l00908"></a><span class="lineno">  908</span> </div>
<div class="line"><a id="l00909" name="l00909"></a><span class="lineno">  909</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaeb929908d2e7fdef2136c20c93377c70">DMA_SxCR_PINCOS</a>, OffsetSize);</div>
<div class="line"><a id="l00910" name="l00910"></a><span class="lineno">  910</span>}</div>
<div class="line"><a id="l00911" name="l00911"></a><span class="lineno">  911</span></div>
<div class="line"><a id="l00929" name="l00929"></a><span class="lineno">  929</span>__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00930" name="l00930"></a><span class="lineno">  930</span>{</div>
<div class="line"><a id="l00931" name="l00931"></a><span class="lineno">  931</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00932" name="l00932"></a><span class="lineno">  932</span> </div>
<div class="line"><a id="l00933" name="l00933"></a><span class="lineno">  933</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaeb929908d2e7fdef2136c20c93377c70">DMA_SxCR_PINCOS</a>));</div>
<div class="line"><a id="l00934" name="l00934"></a><span class="lineno">  934</span>}</div>
<div class="line"><a id="l00935" name="l00935"></a><span class="lineno">  935</span></div>
<div class="line"><a id="l00956" name="l00956"></a><span class="lineno">  956</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetStreamPriorityLevel(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t  Priority)</div>
<div class="line"><a id="l00957" name="l00957"></a><span class="lineno">  957</span>{</div>
<div class="line"><a id="l00958" name="l00958"></a><span class="lineno">  958</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00959" name="l00959"></a><span class="lineno">  959</span> </div>
<div class="line"><a id="l00960" name="l00960"></a><span class="lineno">  960</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga14c115d71a4e3b3c4da360108288154c">DMA_SxCR_PL</a>, Priority);</div>
<div class="line"><a id="l00961" name="l00961"></a><span class="lineno">  961</span>}</div>
<div class="line"><a id="l00962" name="l00962"></a><span class="lineno">  962</span></div>
<div class="line"><a id="l00982" name="l00982"></a><span class="lineno">  982</span>__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l00983" name="l00983"></a><span class="lineno">  983</span>{</div>
<div class="line"><a id="l00984" name="l00984"></a><span class="lineno">  984</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l00985" name="l00985"></a><span class="lineno">  985</span> </div>
<div class="line"><a id="l00986" name="l00986"></a><span class="lineno">  986</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga14c115d71a4e3b3c4da360108288154c">DMA_SxCR_PL</a>));</div>
<div class="line"><a id="l00987" name="l00987"></a><span class="lineno">  987</span>}</div>
<div class="line"><a id="l00988" name="l00988"></a><span class="lineno">  988</span></div>
<div class="line"><a id="l01004" name="l01004"></a><span class="lineno"> 1004</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableBufferableTransfer(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01005" name="l01005"></a><span class="lineno"> 1005</span>{</div>
<div class="line"><a id="l01006" name="l01006"></a><span class="lineno"> 1006</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01007" name="l01007"></a><span class="lineno"> 1007</span> </div>
<div class="line"><a id="l01008" name="l01008"></a><span class="lineno"> 1008</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga40a8216c2ca395553c72b00d087087c6">DMA_SxCR_TRBUFF</a>);</div>
<div class="line"><a id="l01009" name="l01009"></a><span class="lineno"> 1009</span>}</div>
<div class="line"><a id="l01010" name="l01010"></a><span class="lineno"> 1010</span></div>
<div class="line"><a id="l01026" name="l01026"></a><span class="lineno"> 1026</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableBufferableTransfer(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01027" name="l01027"></a><span class="lineno"> 1027</span>{</div>
<div class="line"><a id="l01028" name="l01028"></a><span class="lineno"> 1028</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01029" name="l01029"></a><span class="lineno"> 1029</span> </div>
<div class="line"><a id="l01030" name="l01030"></a><span class="lineno"> 1030</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga40a8216c2ca395553c72b00d087087c6">DMA_SxCR_TRBUFF</a>);</div>
<div class="line"><a id="l01031" name="l01031"></a><span class="lineno"> 1031</span>}</div>
<div class="line"><a id="l01032" name="l01032"></a><span class="lineno"> 1032</span></div>
<div class="line"><a id="l01051" name="l01051"></a><span class="lineno"> 1051</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetDataLength(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t NbData)</div>
<div class="line"><a id="l01052" name="l01052"></a><span class="lineno"> 1052</span>{</div>
<div class="line"><a id="l01053" name="l01053"></a><span class="lineno"> 1053</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01054" name="l01054"></a><span class="lineno"> 1054</span> </div>
<div class="line"><a id="l01055" name="l01055"></a><span class="lineno"> 1055</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;NDTR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga62e0e1a1121885de705e618855ba83b0">DMA_SxNDT</a>, NbData);</div>
<div class="line"><a id="l01056" name="l01056"></a><span class="lineno"> 1056</span>}</div>
<div class="line"><a id="l01057" name="l01057"></a><span class="lineno"> 1057</span></div>
<div class="line"><a id="l01075" name="l01075"></a><span class="lineno"> 1075</span>__STATIC_INLINE uint32_t LL_DMA_GetDataLength(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01076" name="l01076"></a><span class="lineno"> 1076</span>{</div>
<div class="line"><a id="l01077" name="l01077"></a><span class="lineno"> 1077</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01078" name="l01078"></a><span class="lineno"> 1078</span> </div>
<div class="line"><a id="l01079" name="l01079"></a><span class="lineno"> 1079</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;NDTR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga62e0e1a1121885de705e618855ba83b0">DMA_SxNDT</a>));</div>
<div class="line"><a id="l01080" name="l01080"></a><span class="lineno"> 1080</span>}</div>
<div class="line"><a id="l01238" name="l01238"></a><span class="lineno"> 1238</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetPeriphRequest(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t Request)</div>
<div class="line"><a id="l01239" name="l01239"></a><span class="lineno"> 1239</span>{</div>
<div class="line"><a id="l01240" name="l01240"></a><span class="lineno"> 1240</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a_m_u_x___channel___type_def.html">DMAMUX_Channel_TypeDef</a> *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))-&gt;CCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga429e04913f0ea2ec973e5e82c0264766">DMAMUX_CxCR_DMAREQ_ID</a>, Request);</div>
<div class="line"><a id="l01241" name="l01241"></a><span class="lineno"> 1241</span>}</div>
<div class="line"><a id="l01242" name="l01242"></a><span class="lineno"> 1242</span></div>
<div class="line"><a id="l01399" name="l01399"></a><span class="lineno"> 1399</span>__STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01400" name="l01400"></a><span class="lineno"> 1400</span>{</div>
<div class="line"><a id="l01401" name="l01401"></a><span class="lineno"> 1401</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a_m_u_x___channel___type_def.html">DMAMUX_Channel_TypeDef</a> *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))-&gt;CCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga429e04913f0ea2ec973e5e82c0264766">DMAMUX_CxCR_DMAREQ_ID</a>));</div>
<div class="line"><a id="l01402" name="l01402"></a><span class="lineno"> 1402</span>}</div>
<div class="line"><a id="l01403" name="l01403"></a><span class="lineno"> 1403</span></div>
<div class="line"><a id="l01424" name="l01424"></a><span class="lineno"> 1424</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetMemoryBurstxfer(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t Mburst)</div>
<div class="line"><a id="l01425" name="l01425"></a><span class="lineno"> 1425</span>{</div>
<div class="line"><a id="l01426" name="l01426"></a><span class="lineno"> 1426</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01427" name="l01427"></a><span class="lineno"> 1427</span> </div>
<div class="line"><a id="l01428" name="l01428"></a><span class="lineno"> 1428</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5c1174bff38faf5d87b71521bce8f84f">DMA_SxCR_MBURST</a>, Mburst);</div>
<div class="line"><a id="l01429" name="l01429"></a><span class="lineno"> 1429</span>}</div>
<div class="line"><a id="l01430" name="l01430"></a><span class="lineno"> 1430</span></div>
<div class="line"><a id="l01450" name="l01450"></a><span class="lineno"> 1450</span>__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01451" name="l01451"></a><span class="lineno"> 1451</span>{</div>
<div class="line"><a id="l01452" name="l01452"></a><span class="lineno"> 1452</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01453" name="l01453"></a><span class="lineno"> 1453</span> </div>
<div class="line"><a id="l01454" name="l01454"></a><span class="lineno"> 1454</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5c1174bff38faf5d87b71521bce8f84f">DMA_SxCR_MBURST</a>));</div>
<div class="line"><a id="l01455" name="l01455"></a><span class="lineno"> 1455</span>}</div>
<div class="line"><a id="l01456" name="l01456"></a><span class="lineno"> 1456</span></div>
<div class="line"><a id="l01477" name="l01477"></a><span class="lineno"> 1477</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetPeriphBurstxfer(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t Pburst)</div>
<div class="line"><a id="l01478" name="l01478"></a><span class="lineno"> 1478</span>{</div>
<div class="line"><a id="l01479" name="l01479"></a><span class="lineno"> 1479</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01480" name="l01480"></a><span class="lineno"> 1480</span> </div>
<div class="line"><a id="l01481" name="l01481"></a><span class="lineno"> 1481</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga502380abb155eb3b37a2ca9359e2da2e">DMA_SxCR_PBURST</a>, Pburst);</div>
<div class="line"><a id="l01482" name="l01482"></a><span class="lineno"> 1482</span>}</div>
<div class="line"><a id="l01483" name="l01483"></a><span class="lineno"> 1483</span></div>
<div class="line"><a id="l01503" name="l01503"></a><span class="lineno"> 1503</span>__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01504" name="l01504"></a><span class="lineno"> 1504</span>{</div>
<div class="line"><a id="l01505" name="l01505"></a><span class="lineno"> 1505</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01506" name="l01506"></a><span class="lineno"> 1506</span> </div>
<div class="line"><a id="l01507" name="l01507"></a><span class="lineno"> 1507</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga502380abb155eb3b37a2ca9359e2da2e">DMA_SxCR_PBURST</a>));</div>
<div class="line"><a id="l01508" name="l01508"></a><span class="lineno"> 1508</span>}</div>
<div class="line"><a id="l01509" name="l01509"></a><span class="lineno"> 1509</span></div>
<div class="line"><a id="l01528" name="l01528"></a><span class="lineno"> 1528</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetCurrentTargetMem(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t CurrentMemory)</div>
<div class="line"><a id="l01529" name="l01529"></a><span class="lineno"> 1529</span>{</div>
<div class="line"><a id="l01530" name="l01530"></a><span class="lineno"> 1530</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01531" name="l01531"></a><span class="lineno"> 1531</span> </div>
<div class="line"><a id="l01532" name="l01532"></a><span class="lineno"> 1532</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadd36c677ee53f56dc408cd549e64cf7d">DMA_SxCR_CT</a>, CurrentMemory);</div>
<div class="line"><a id="l01533" name="l01533"></a><span class="lineno"> 1533</span>}</div>
<div class="line"><a id="l01534" name="l01534"></a><span class="lineno"> 1534</span></div>
<div class="line"><a id="l01552" name="l01552"></a><span class="lineno"> 1552</span>__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01553" name="l01553"></a><span class="lineno"> 1553</span>{</div>
<div class="line"><a id="l01554" name="l01554"></a><span class="lineno"> 1554</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01555" name="l01555"></a><span class="lineno"> 1555</span> </div>
<div class="line"><a id="l01556" name="l01556"></a><span class="lineno"> 1556</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadd36c677ee53f56dc408cd549e64cf7d">DMA_SxCR_CT</a>));</div>
<div class="line"><a id="l01557" name="l01557"></a><span class="lineno"> 1557</span>}</div>
<div class="line"><a id="l01558" name="l01558"></a><span class="lineno"> 1558</span></div>
<div class="line"><a id="l01574" name="l01574"></a><span class="lineno"> 1574</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableDoubleBufferMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01575" name="l01575"></a><span class="lineno"> 1575</span>{</div>
<div class="line"><a id="l01576" name="l01576"></a><span class="lineno"> 1576</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01577" name="l01577"></a><span class="lineno"> 1577</span> </div>
<div class="line"><a id="l01578" name="l01578"></a><span class="lineno"> 1578</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497">DMA_SxCR_DBM</a>);</div>
<div class="line"><a id="l01579" name="l01579"></a><span class="lineno"> 1579</span>}</div>
<div class="line"><a id="l01580" name="l01580"></a><span class="lineno"> 1580</span></div>
<div class="line"><a id="l01596" name="l01596"></a><span class="lineno"> 1596</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableDoubleBufferMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01597" name="l01597"></a><span class="lineno"> 1597</span>{</div>
<div class="line"><a id="l01598" name="l01598"></a><span class="lineno"> 1598</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01599" name="l01599"></a><span class="lineno"> 1599</span> </div>
<div class="line"><a id="l01600" name="l01600"></a><span class="lineno"> 1600</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497">DMA_SxCR_DBM</a>);</div>
<div class="line"><a id="l01601" name="l01601"></a><span class="lineno"> 1601</span>}</div>
<div class="line"><a id="l01602" name="l01602"></a><span class="lineno"> 1602</span></div>
<div class="line"><a id="l01618" name="l01618"></a><span class="lineno"> 1618</span>__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01619" name="l01619"></a><span class="lineno"> 1619</span>{</div>
<div class="line"><a id="l01620" name="l01620"></a><span class="lineno"> 1620</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01621" name="l01621"></a><span class="lineno"> 1621</span> </div>
<div class="line"><a id="l01622" name="l01622"></a><span class="lineno"> 1622</span>  <span class="keywordflow">return</span> ((READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497">DMA_SxCR_DBM</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497">DMA_SxCR_DBM</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l01623" name="l01623"></a><span class="lineno"> 1623</span>}</div>
<div class="line"><a id="l01624" name="l01624"></a><span class="lineno"> 1624</span></div>
<div class="line"><a id="l01646" name="l01646"></a><span class="lineno"> 1646</span>__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01647" name="l01647"></a><span class="lineno"> 1647</span>{</div>
<div class="line"><a id="l01648" name="l01648"></a><span class="lineno"> 1648</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01649" name="l01649"></a><span class="lineno"> 1649</span> </div>
<div class="line"><a id="l01650" name="l01650"></a><span class="lineno"> 1650</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga56094479dc9b173b00ccfb199d8a2853">DMA_SxFCR_FS</a>));</div>
<div class="line"><a id="l01651" name="l01651"></a><span class="lineno"> 1651</span>}</div>
<div class="line"><a id="l01652" name="l01652"></a><span class="lineno"> 1652</span></div>
<div class="line"><a id="l01668" name="l01668"></a><span class="lineno"> 1668</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableFifoMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01669" name="l01669"></a><span class="lineno"> 1669</span>{</div>
<div class="line"><a id="l01670" name="l01670"></a><span class="lineno"> 1670</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01671" name="l01671"></a><span class="lineno"> 1671</span> </div>
<div class="line"><a id="l01672" name="l01672"></a><span class="lineno"> 1672</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga89406bb954742665691c0ac2f8d95ec9">DMA_SxFCR_DMDIS</a>);</div>
<div class="line"><a id="l01673" name="l01673"></a><span class="lineno"> 1673</span>}</div>
<div class="line"><a id="l01674" name="l01674"></a><span class="lineno"> 1674</span></div>
<div class="line"><a id="l01690" name="l01690"></a><span class="lineno"> 1690</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableFifoMode(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01691" name="l01691"></a><span class="lineno"> 1691</span>{</div>
<div class="line"><a id="l01692" name="l01692"></a><span class="lineno"> 1692</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01693" name="l01693"></a><span class="lineno"> 1693</span> </div>
<div class="line"><a id="l01694" name="l01694"></a><span class="lineno"> 1694</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga89406bb954742665691c0ac2f8d95ec9">DMA_SxFCR_DMDIS</a>);</div>
<div class="line"><a id="l01695" name="l01695"></a><span class="lineno"> 1695</span>}</div>
<div class="line"><a id="l01696" name="l01696"></a><span class="lineno"> 1696</span></div>
<div class="line"><a id="l01717" name="l01717"></a><span class="lineno"> 1717</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetFIFOThreshold(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t Threshold)</div>
<div class="line"><a id="l01718" name="l01718"></a><span class="lineno"> 1718</span>{</div>
<div class="line"><a id="l01719" name="l01719"></a><span class="lineno"> 1719</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01720" name="l01720"></a><span class="lineno"> 1720</span> </div>
<div class="line"><a id="l01721" name="l01721"></a><span class="lineno"> 1721</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga44c16978164026a81f5b07280e800e7f">DMA_SxFCR_FTH</a>, Threshold);</div>
<div class="line"><a id="l01722" name="l01722"></a><span class="lineno"> 1722</span>}</div>
<div class="line"><a id="l01723" name="l01723"></a><span class="lineno"> 1723</span></div>
<div class="line"><a id="l01743" name="l01743"></a><span class="lineno"> 1743</span>__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01744" name="l01744"></a><span class="lineno"> 1744</span>{</div>
<div class="line"><a id="l01745" name="l01745"></a><span class="lineno"> 1745</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01746" name="l01746"></a><span class="lineno"> 1746</span> </div>
<div class="line"><a id="l01747" name="l01747"></a><span class="lineno"> 1747</span>  <span class="keywordflow">return</span> (READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga44c16978164026a81f5b07280e800e7f">DMA_SxFCR_FTH</a>));</div>
<div class="line"><a id="l01748" name="l01748"></a><span class="lineno"> 1748</span>}</div>
<div class="line"><a id="l01749" name="l01749"></a><span class="lineno"> 1749</span></div>
<div class="line"><a id="l01774" name="l01774"></a><span class="lineno"> 1774</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ConfigFifo(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)</div>
<div class="line"><a id="l01775" name="l01775"></a><span class="lineno"> 1775</span>{</div>
<div class="line"><a id="l01776" name="l01776"></a><span class="lineno"> 1776</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01777" name="l01777"></a><span class="lineno"> 1777</span> </div>
<div class="line"><a id="l01778" name="l01778"></a><span class="lineno"> 1778</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga44c16978164026a81f5b07280e800e7f">DMA_SxFCR_FTH</a> | <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga89406bb954742665691c0ac2f8d95ec9">DMA_SxFCR_DMDIS</a>, FifoMode | FifoThreshold);</div>
<div class="line"><a id="l01779" name="l01779"></a><span class="lineno"> 1779</span>}</div>
<div class="line"><a id="l01780" name="l01780"></a><span class="lineno"> 1780</span></div>
<div class="line"><a id="l01804" name="l01804"></a><span class="lineno"> 1804</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ConfigAddresses(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)</div>
<div class="line"><a id="l01805" name="l01805"></a><span class="lineno"> 1805</span>{</div>
<div class="line"><a id="l01806" name="l01806"></a><span class="lineno"> 1806</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01807" name="l01807"></a><span class="lineno"> 1807</span> </div>
<div class="line"><a id="l01808" name="l01808"></a><span class="lineno"> 1808</span>  <span class="comment">/* Direction Memory to Periph */</span></div>
<div class="line"><a id="l01809" name="l01809"></a><span class="lineno"> 1809</span>  <span class="keywordflow">if</span> (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)</div>
<div class="line"><a id="l01810" name="l01810"></a><span class="lineno"> 1810</span>  {</div>
<div class="line"><a id="l01811" name="l01811"></a><span class="lineno"> 1811</span>    WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M0AR, SrcAddress);</div>
<div class="line"><a id="l01812" name="l01812"></a><span class="lineno"> 1812</span>    WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;PAR, DstAddress);</div>
<div class="line"><a id="l01813" name="l01813"></a><span class="lineno"> 1813</span>  }</div>
<div class="line"><a id="l01814" name="l01814"></a><span class="lineno"> 1814</span>  <span class="comment">/* Direction Periph to Memory and Memory to Memory */</span></div>
<div class="line"><a id="l01815" name="l01815"></a><span class="lineno"> 1815</span>  <span class="keywordflow">else</span></div>
<div class="line"><a id="l01816" name="l01816"></a><span class="lineno"> 1816</span>  {</div>
<div class="line"><a id="l01817" name="l01817"></a><span class="lineno"> 1817</span>    WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;PAR, SrcAddress);</div>
<div class="line"><a id="l01818" name="l01818"></a><span class="lineno"> 1818</span>    WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M0AR, DstAddress);</div>
<div class="line"><a id="l01819" name="l01819"></a><span class="lineno"> 1819</span>  }</div>
<div class="line"><a id="l01820" name="l01820"></a><span class="lineno"> 1820</span>}</div>
<div class="line"><a id="l01821" name="l01821"></a><span class="lineno"> 1821</span></div>
<div class="line"><a id="l01840" name="l01840"></a><span class="lineno"> 1840</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetMemoryAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t MemoryAddress)</div>
<div class="line"><a id="l01841" name="l01841"></a><span class="lineno"> 1841</span>{</div>
<div class="line"><a id="l01842" name="l01842"></a><span class="lineno"> 1842</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01843" name="l01843"></a><span class="lineno"> 1843</span> </div>
<div class="line"><a id="l01844" name="l01844"></a><span class="lineno"> 1844</span>  WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M0AR, MemoryAddress);</div>
<div class="line"><a id="l01845" name="l01845"></a><span class="lineno"> 1845</span>}</div>
<div class="line"><a id="l01846" name="l01846"></a><span class="lineno"> 1846</span></div>
<div class="line"><a id="l01865" name="l01865"></a><span class="lineno"> 1865</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetPeriphAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t PeriphAddress)</div>
<div class="line"><a id="l01866" name="l01866"></a><span class="lineno"> 1866</span>{</div>
<div class="line"><a id="l01867" name="l01867"></a><span class="lineno"> 1867</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01868" name="l01868"></a><span class="lineno"> 1868</span> </div>
<div class="line"><a id="l01869" name="l01869"></a><span class="lineno"> 1869</span>  WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;PAR, PeriphAddress);</div>
<div class="line"><a id="l01870" name="l01870"></a><span class="lineno"> 1870</span>}</div>
<div class="line"><a id="l01871" name="l01871"></a><span class="lineno"> 1871</span></div>
<div class="line"><a id="l01888" name="l01888"></a><span class="lineno"> 1888</span>__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01889" name="l01889"></a><span class="lineno"> 1889</span>{</div>
<div class="line"><a id="l01890" name="l01890"></a><span class="lineno"> 1890</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01891" name="l01891"></a><span class="lineno"> 1891</span> </div>
<div class="line"><a id="l01892" name="l01892"></a><span class="lineno"> 1892</span>  <span class="keywordflow">return</span> (READ_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M0AR));</div>
<div class="line"><a id="l01893" name="l01893"></a><span class="lineno"> 1893</span>}</div>
<div class="line"><a id="l01894" name="l01894"></a><span class="lineno"> 1894</span></div>
<div class="line"><a id="l01911" name="l01911"></a><span class="lineno"> 1911</span>__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01912" name="l01912"></a><span class="lineno"> 1912</span>{</div>
<div class="line"><a id="l01913" name="l01913"></a><span class="lineno"> 1913</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01914" name="l01914"></a><span class="lineno"> 1914</span> </div>
<div class="line"><a id="l01915" name="l01915"></a><span class="lineno"> 1915</span>  <span class="keywordflow">return</span> (READ_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;PAR));</div>
<div class="line"><a id="l01916" name="l01916"></a><span class="lineno"> 1916</span>}</div>
<div class="line"><a id="l01917" name="l01917"></a><span class="lineno"> 1917</span></div>
<div class="line"><a id="l01936" name="l01936"></a><span class="lineno"> 1936</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetM2MSrcAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t MemoryAddress)</div>
<div class="line"><a id="l01937" name="l01937"></a><span class="lineno"> 1937</span>{</div>
<div class="line"><a id="l01938" name="l01938"></a><span class="lineno"> 1938</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01939" name="l01939"></a><span class="lineno"> 1939</span> </div>
<div class="line"><a id="l01940" name="l01940"></a><span class="lineno"> 1940</span>  WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;PAR, MemoryAddress);</div>
<div class="line"><a id="l01941" name="l01941"></a><span class="lineno"> 1941</span>}</div>
<div class="line"><a id="l01942" name="l01942"></a><span class="lineno"> 1942</span></div>
<div class="line"><a id="l01961" name="l01961"></a><span class="lineno"> 1961</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetM2MDstAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t MemoryAddress)</div>
<div class="line"><a id="l01962" name="l01962"></a><span class="lineno"> 1962</span>{</div>
<div class="line"><a id="l01963" name="l01963"></a><span class="lineno"> 1963</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01964" name="l01964"></a><span class="lineno"> 1964</span> </div>
<div class="line"><a id="l01965" name="l01965"></a><span class="lineno"> 1965</span>  WRITE_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M0AR, MemoryAddress);</div>
<div class="line"><a id="l01966" name="l01966"></a><span class="lineno"> 1966</span>}</div>
<div class="line"><a id="l01967" name="l01967"></a><span class="lineno"> 1967</span></div>
<div class="line"><a id="l01984" name="l01984"></a><span class="lineno"> 1984</span>__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l01985" name="l01985"></a><span class="lineno"> 1985</span>{</div>
<div class="line"><a id="l01986" name="l01986"></a><span class="lineno"> 1986</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l01987" name="l01987"></a><span class="lineno"> 1987</span> </div>
<div class="line"><a id="l01988" name="l01988"></a><span class="lineno"> 1988</span>  <span class="keywordflow">return</span> (READ_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;PAR));</div>
<div class="line"><a id="l01989" name="l01989"></a><span class="lineno"> 1989</span>}</div>
<div class="line"><a id="l01990" name="l01990"></a><span class="lineno"> 1990</span></div>
<div class="line"><a id="l02007" name="l02007"></a><span class="lineno"> 2007</span>__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l02008" name="l02008"></a><span class="lineno"> 2008</span>{</div>
<div class="line"><a id="l02009" name="l02009"></a><span class="lineno"> 2009</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l02010" name="l02010"></a><span class="lineno"> 2010</span> </div>
<div class="line"><a id="l02011" name="l02011"></a><span class="lineno"> 2011</span>  <span class="keywordflow">return</span> (READ_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M0AR));</div>
<div class="line"><a id="l02012" name="l02012"></a><span class="lineno"> 2012</span>}</div>
<div class="line"><a id="l02013" name="l02013"></a><span class="lineno"> 2013</span></div>
<div class="line"><a id="l02030" name="l02030"></a><span class="lineno"> 2030</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_SetMemory1Address(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, uint32_t Address)</div>
<div class="line"><a id="l02031" name="l02031"></a><span class="lineno"> 2031</span>{</div>
<div class="line"><a id="l02032" name="l02032"></a><span class="lineno"> 2032</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l02033" name="l02033"></a><span class="lineno"> 2033</span> </div>
<div class="line"><a id="l02034" name="l02034"></a><span class="lineno"> 2034</span>  MODIFY_REG(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M1AR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae057bfb6e5d7b553b668a050fcdb152d">DMA_SxM1AR_M1A</a>, Address);</div>
<div class="line"><a id="l02035" name="l02035"></a><span class="lineno"> 2035</span>}</div>
<div class="line"><a id="l02036" name="l02036"></a><span class="lineno"> 2036</span></div>
<div class="line"><a id="l02052" name="l02052"></a><span class="lineno"> 2052</span>__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l02053" name="l02053"></a><span class="lineno"> 2053</span>{</div>
<div class="line"><a id="l02054" name="l02054"></a><span class="lineno"> 2054</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l02055" name="l02055"></a><span class="lineno"> 2055</span> </div>
<div class="line"><a id="l02056" name="l02056"></a><span class="lineno"> 2056</span>  <span class="keywordflow">return</span> (((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;M1AR);</div>
<div class="line"><a id="l02057" name="l02057"></a><span class="lineno"> 2057</span>}</div>
<div class="line"><a id="l02058" name="l02058"></a><span class="lineno"> 2058</span></div>
<div class="line"><a id="l02062" name="l02062"></a><span class="lineno"> 2062</span></div>
<div class="line"><a id="l02066" name="l02066"></a><span class="lineno"> 2066</span></div>
<div class="line"><a id="l02073" name="l02073"></a><span class="lineno"> 2073</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02074" name="l02074"></a><span class="lineno"> 2074</span>{</div>
<div class="line"><a id="l02075" name="l02075"></a><span class="lineno"> 2075</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6181727d13abbc46283ff22ce359e3b9">DMA_LISR_HTIF0</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6181727d13abbc46283ff22ce359e3b9">DMA_LISR_HTIF0</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02076" name="l02076"></a><span class="lineno"> 2076</span>}</div>
<div class="line"><a id="l02077" name="l02077"></a><span class="lineno"> 2077</span></div>
<div class="line"><a id="l02084" name="l02084"></a><span class="lineno"> 2084</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02085" name="l02085"></a><span class="lineno"> 2085</span>{</div>
<div class="line"><a id="l02086" name="l02086"></a><span class="lineno"> 2086</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga04304a9f8891e325247c0aaa4c9fac72">DMA_LISR_HTIF1</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga04304a9f8891e325247c0aaa4c9fac72">DMA_LISR_HTIF1</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02087" name="l02087"></a><span class="lineno"> 2087</span>}</div>
<div class="line"><a id="l02088" name="l02088"></a><span class="lineno"> 2088</span></div>
<div class="line"><a id="l02095" name="l02095"></a><span class="lineno"> 2095</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02096" name="l02096"></a><span class="lineno"> 2096</span>{</div>
<div class="line"><a id="l02097" name="l02097"></a><span class="lineno"> 2097</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ca25185d14a1f0c208ec8ceadc787a6">DMA_LISR_HTIF2</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ca25185d14a1f0c208ec8ceadc787a6">DMA_LISR_HTIF2</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02098" name="l02098"></a><span class="lineno"> 2098</span>}</div>
<div class="line"><a id="l02099" name="l02099"></a><span class="lineno"> 2099</span></div>
<div class="line"><a id="l02106" name="l02106"></a><span class="lineno"> 2106</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02107" name="l02107"></a><span class="lineno"> 2107</span>{</div>
<div class="line"><a id="l02108" name="l02108"></a><span class="lineno"> 2108</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa10c891ee2ec333b7f87eea5886d574f">DMA_LISR_HTIF3</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa10c891ee2ec333b7f87eea5886d574f">DMA_LISR_HTIF3</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02109" name="l02109"></a><span class="lineno"> 2109</span>}</div>
<div class="line"><a id="l02110" name="l02110"></a><span class="lineno"> 2110</span></div>
<div class="line"><a id="l02117" name="l02117"></a><span class="lineno"> 2117</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02118" name="l02118"></a><span class="lineno"> 2118</span>{</div>
<div class="line"><a id="l02119" name="l02119"></a><span class="lineno"> 2119</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadba8d24329c676d70560eda0b8c1e5b0">DMA_HISR_HTIF4</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadba8d24329c676d70560eda0b8c1e5b0">DMA_HISR_HTIF4</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02120" name="l02120"></a><span class="lineno"> 2120</span>}</div>
<div class="line"><a id="l02121" name="l02121"></a><span class="lineno"> 2121</span></div>
<div class="line"><a id="l02128" name="l02128"></a><span class="lineno"> 2128</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02129" name="l02129"></a><span class="lineno"> 2129</span>{</div>
<div class="line"><a id="l02130" name="l02130"></a><span class="lineno"> 2130</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga8617bf8160d1027879ffd354e04908d9">DMA_HISR_HTIF5</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga8617bf8160d1027879ffd354e04908d9">DMA_HISR_HTIF5</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02131" name="l02131"></a><span class="lineno"> 2131</span>}</div>
<div class="line"><a id="l02132" name="l02132"></a><span class="lineno"> 2132</span></div>
<div class="line"><a id="l02139" name="l02139"></a><span class="lineno"> 2139</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02140" name="l02140"></a><span class="lineno"> 2140</span>{</div>
<div class="line"><a id="l02141" name="l02141"></a><span class="lineno"> 2141</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0d39c14138e9ff216c203b288137144b">DMA_HISR_HTIF6</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0d39c14138e9ff216c203b288137144b">DMA_HISR_HTIF6</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02142" name="l02142"></a><span class="lineno"> 2142</span>}</div>
<div class="line"><a id="l02143" name="l02143"></a><span class="lineno"> 2143</span></div>
<div class="line"><a id="l02150" name="l02150"></a><span class="lineno"> 2150</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02151" name="l02151"></a><span class="lineno"> 2151</span>{</div>
<div class="line"><a id="l02152" name="l02152"></a><span class="lineno"> 2152</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf535d1a3209d2e2e0e616e2d7501525d">DMA_HISR_HTIF7</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf535d1a3209d2e2e0e616e2d7501525d">DMA_HISR_HTIF7</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02153" name="l02153"></a><span class="lineno"> 2153</span>}</div>
<div class="line"><a id="l02154" name="l02154"></a><span class="lineno"> 2154</span></div>
<div class="line"><a id="l02161" name="l02161"></a><span class="lineno"> 2161</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02162" name="l02162"></a><span class="lineno"> 2162</span>{</div>
<div class="line"><a id="l02163" name="l02163"></a><span class="lineno"> 2163</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadbc3f7e52c0688bed4b71fa37666901d">DMA_LISR_TCIF0</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadbc3f7e52c0688bed4b71fa37666901d">DMA_LISR_TCIF0</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02164" name="l02164"></a><span class="lineno"> 2164</span>}</div>
<div class="line"><a id="l02165" name="l02165"></a><span class="lineno"> 2165</span></div>
<div class="line"><a id="l02172" name="l02172"></a><span class="lineno"> 2172</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02173" name="l02173"></a><span class="lineno"> 2173</span>{</div>
<div class="line"><a id="l02174" name="l02174"></a><span class="lineno"> 2174</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae02aec39ded937b3ce816d3df4520d9b">DMA_LISR_TCIF1</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae02aec39ded937b3ce816d3df4520d9b">DMA_LISR_TCIF1</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02175" name="l02175"></a><span class="lineno"> 2175</span>}</div>
<div class="line"><a id="l02176" name="l02176"></a><span class="lineno"> 2176</span></div>
<div class="line"><a id="l02183" name="l02183"></a><span class="lineno"> 2183</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02184" name="l02184"></a><span class="lineno"> 2184</span>{</div>
<div class="line"><a id="l02185" name="l02185"></a><span class="lineno"> 2185</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf21350cce8c4cb5d7c6fcf5edc930cf8">DMA_LISR_TCIF2</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf21350cce8c4cb5d7c6fcf5edc930cf8">DMA_LISR_TCIF2</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02186" name="l02186"></a><span class="lineno"> 2186</span>}</div>
<div class="line"><a id="l02187" name="l02187"></a><span class="lineno"> 2187</span></div>
<div class="line"><a id="l02194" name="l02194"></a><span class="lineno"> 2194</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02195" name="l02195"></a><span class="lineno"> 2195</span>{</div>
<div class="line"><a id="l02196" name="l02196"></a><span class="lineno"> 2196</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga44e5bf8adbb2646d325cba8d5dd670d8">DMA_LISR_TCIF3</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga44e5bf8adbb2646d325cba8d5dd670d8">DMA_LISR_TCIF3</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02197" name="l02197"></a><span class="lineno"> 2197</span>}</div>
<div class="line"><a id="l02198" name="l02198"></a><span class="lineno"> 2198</span></div>
<div class="line"><a id="l02205" name="l02205"></a><span class="lineno"> 2205</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02206" name="l02206"></a><span class="lineno"> 2206</span>{</div>
<div class="line"><a id="l02207" name="l02207"></a><span class="lineno"> 2207</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gafcce25c245499f9e62cb757e1871d973">DMA_HISR_TCIF4</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gafcce25c245499f9e62cb757e1871d973">DMA_HISR_TCIF4</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02208" name="l02208"></a><span class="lineno"> 2208</span>}</div>
<div class="line"><a id="l02209" name="l02209"></a><span class="lineno"> 2209</span></div>
<div class="line"><a id="l02216" name="l02216"></a><span class="lineno"> 2216</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02217" name="l02217"></a><span class="lineno"> 2217</span>{</div>
<div class="line"><a id="l02218" name="l02218"></a><span class="lineno"> 2218</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga64f15eaf1dd30450d1d35ee517507321">DMA_HISR_TCIF5</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga64f15eaf1dd30450d1d35ee517507321">DMA_HISR_TCIF5</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02219" name="l02219"></a><span class="lineno"> 2219</span>}</div>
<div class="line"><a id="l02220" name="l02220"></a><span class="lineno"> 2220</span></div>
<div class="line"><a id="l02227" name="l02227"></a><span class="lineno"> 2227</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02228" name="l02228"></a><span class="lineno"> 2228</span>{</div>
<div class="line"><a id="l02229" name="l02229"></a><span class="lineno"> 2229</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad29468aa609150e241d9ae62c477cf45">DMA_HISR_TCIF6</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad29468aa609150e241d9ae62c477cf45">DMA_HISR_TCIF6</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02230" name="l02230"></a><span class="lineno"> 2230</span>}</div>
<div class="line"><a id="l02231" name="l02231"></a><span class="lineno"> 2231</span></div>
<div class="line"><a id="l02238" name="l02238"></a><span class="lineno"> 2238</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02239" name="l02239"></a><span class="lineno"> 2239</span>{</div>
<div class="line"><a id="l02240" name="l02240"></a><span class="lineno"> 2240</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad20a0a5e103def436d4e329fc0888482">DMA_HISR_TCIF7</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad20a0a5e103def436d4e329fc0888482">DMA_HISR_TCIF7</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02241" name="l02241"></a><span class="lineno"> 2241</span>}</div>
<div class="line"><a id="l02242" name="l02242"></a><span class="lineno"> 2242</span></div>
<div class="line"><a id="l02249" name="l02249"></a><span class="lineno"> 2249</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02250" name="l02250"></a><span class="lineno"> 2250</span>{</div>
<div class="line"><a id="l02251" name="l02251"></a><span class="lineno"> 2251</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad43cdafa5acfcd683b7a2ee8976dd8ba">DMA_LISR_TEIF0</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad43cdafa5acfcd683b7a2ee8976dd8ba">DMA_LISR_TEIF0</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02252" name="l02252"></a><span class="lineno"> 2252</span>}</div>
<div class="line"><a id="l02253" name="l02253"></a><span class="lineno"> 2253</span></div>
<div class="line"><a id="l02260" name="l02260"></a><span class="lineno"> 2260</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02261" name="l02261"></a><span class="lineno"> 2261</span>{</div>
<div class="line"><a id="l02262" name="l02262"></a><span class="lineno"> 2262</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0cd826db0b9ea5544d1a93beb90f8972">DMA_LISR_TEIF1</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0cd826db0b9ea5544d1a93beb90f8972">DMA_LISR_TEIF1</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02263" name="l02263"></a><span class="lineno"> 2263</span>}</div>
<div class="line"><a id="l02264" name="l02264"></a><span class="lineno"> 2264</span></div>
<div class="line"><a id="l02271" name="l02271"></a><span class="lineno"> 2271</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02272" name="l02272"></a><span class="lineno"> 2272</span>{</div>
<div class="line"><a id="l02273" name="l02273"></a><span class="lineno"> 2273</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga74d540802cadde42bdd6debae5d8ab89">DMA_LISR_TEIF2</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga74d540802cadde42bdd6debae5d8ab89">DMA_LISR_TEIF2</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02274" name="l02274"></a><span class="lineno"> 2274</span>}</div>
<div class="line"><a id="l02275" name="l02275"></a><span class="lineno"> 2275</span></div>
<div class="line"><a id="l02282" name="l02282"></a><span class="lineno"> 2282</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02283" name="l02283"></a><span class="lineno"> 2283</span>{</div>
<div class="line"><a id="l02284" name="l02284"></a><span class="lineno"> 2284</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5dfaba3a5db7cdcbddf9ee5974b44c2f">DMA_LISR_TEIF3</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5dfaba3a5db7cdcbddf9ee5974b44c2f">DMA_LISR_TEIF3</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02285" name="l02285"></a><span class="lineno"> 2285</span>}</div>
<div class="line"><a id="l02286" name="l02286"></a><span class="lineno"> 2286</span></div>
<div class="line"><a id="l02293" name="l02293"></a><span class="lineno"> 2293</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02294" name="l02294"></a><span class="lineno"> 2294</span>{</div>
<div class="line"><a id="l02295" name="l02295"></a><span class="lineno"> 2295</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga9005d4b958193fbd701c879eede467c1">DMA_HISR_TEIF4</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga9005d4b958193fbd701c879eede467c1">DMA_HISR_TEIF4</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02296" name="l02296"></a><span class="lineno"> 2296</span>}</div>
<div class="line"><a id="l02297" name="l02297"></a><span class="lineno"> 2297</span></div>
<div class="line"><a id="l02304" name="l02304"></a><span class="lineno"> 2304</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02305" name="l02305"></a><span class="lineno"> 2305</span>{</div>
<div class="line"><a id="l02306" name="l02306"></a><span class="lineno"> 2306</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf16fb0e5d87f704c89824f961bfb7637">DMA_HISR_TEIF5</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf16fb0e5d87f704c89824f961bfb7637">DMA_HISR_TEIF5</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02307" name="l02307"></a><span class="lineno"> 2307</span>}</div>
<div class="line"><a id="l02308" name="l02308"></a><span class="lineno"> 2308</span></div>
<div class="line"><a id="l02315" name="l02315"></a><span class="lineno"> 2315</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02316" name="l02316"></a><span class="lineno"> 2316</span>{</div>
<div class="line"><a id="l02317" name="l02317"></a><span class="lineno"> 2317</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1a7ec01955fb504a5aa4f9f16a9ac52c">DMA_HISR_TEIF6</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1a7ec01955fb504a5aa4f9f16a9ac52c">DMA_HISR_TEIF6</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02318" name="l02318"></a><span class="lineno"> 2318</span>}</div>
<div class="line"><a id="l02319" name="l02319"></a><span class="lineno"> 2319</span></div>
<div class="line"><a id="l02326" name="l02326"></a><span class="lineno"> 2326</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02327" name="l02327"></a><span class="lineno"> 2327</span>{</div>
<div class="line"><a id="l02328" name="l02328"></a><span class="lineno"> 2328</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga960f094539b5afc7f9d5e45b7909afe6">DMA_HISR_TEIF7</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga960f094539b5afc7f9d5e45b7909afe6">DMA_HISR_TEIF7</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02329" name="l02329"></a><span class="lineno"> 2329</span>}</div>
<div class="line"><a id="l02330" name="l02330"></a><span class="lineno"> 2330</span></div>
<div class="line"><a id="l02337" name="l02337"></a><span class="lineno"> 2337</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02338" name="l02338"></a><span class="lineno"> 2338</span>{</div>
<div class="line"><a id="l02339" name="l02339"></a><span class="lineno"> 2339</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga72de97ebc9d063dceb38bada91c44878">DMA_LISR_DMEIF0</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga72de97ebc9d063dceb38bada91c44878">DMA_LISR_DMEIF0</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02340" name="l02340"></a><span class="lineno"> 2340</span>}</div>
<div class="line"><a id="l02341" name="l02341"></a><span class="lineno"> 2341</span></div>
<div class="line"><a id="l02348" name="l02348"></a><span class="lineno"> 2348</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02349" name="l02349"></a><span class="lineno"> 2349</span>{</div>
<div class="line"><a id="l02350" name="l02350"></a><span class="lineno"> 2350</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa4903814bfc12dd6193416374fbddf8c">DMA_LISR_DMEIF1</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa4903814bfc12dd6193416374fbddf8c">DMA_LISR_DMEIF1</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02351" name="l02351"></a><span class="lineno"> 2351</span>}</div>
<div class="line"><a id="l02352" name="l02352"></a><span class="lineno"> 2352</span></div>
<div class="line"><a id="l02359" name="l02359"></a><span class="lineno"> 2359</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02360" name="l02360"></a><span class="lineno"> 2360</span>{</div>
<div class="line"><a id="l02361" name="l02361"></a><span class="lineno"> 2361</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gabc7edcd7404f0dcf19a724dfad22026a">DMA_LISR_DMEIF2</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gabc7edcd7404f0dcf19a724dfad22026a">DMA_LISR_DMEIF2</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02362" name="l02362"></a><span class="lineno"> 2362</span>}</div>
<div class="line"><a id="l02363" name="l02363"></a><span class="lineno"> 2363</span></div>
<div class="line"><a id="l02370" name="l02370"></a><span class="lineno"> 2370</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02371" name="l02371"></a><span class="lineno"> 2371</span>{</div>
<div class="line"><a id="l02372" name="l02372"></a><span class="lineno"> 2372</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga01fd1397b41221f5bdf6f107cb92e196">DMA_LISR_DMEIF3</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga01fd1397b41221f5bdf6f107cb92e196">DMA_LISR_DMEIF3</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02373" name="l02373"></a><span class="lineno"> 2373</span>}</div>
<div class="line"><a id="l02374" name="l02374"></a><span class="lineno"> 2374</span></div>
<div class="line"><a id="l02381" name="l02381"></a><span class="lineno"> 2381</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02382" name="l02382"></a><span class="lineno"> 2382</span>{</div>
<div class="line"><a id="l02383" name="l02383"></a><span class="lineno"> 2383</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf716f1bc12ea70f49802d84fb77646e8">DMA_HISR_DMEIF4</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf716f1bc12ea70f49802d84fb77646e8">DMA_HISR_DMEIF4</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02384" name="l02384"></a><span class="lineno"> 2384</span>}</div>
<div class="line"><a id="l02385" name="l02385"></a><span class="lineno"> 2385</span></div>
<div class="line"><a id="l02392" name="l02392"></a><span class="lineno"> 2392</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02393" name="l02393"></a><span class="lineno"> 2393</span>{</div>
<div class="line"><a id="l02394" name="l02394"></a><span class="lineno"> 2394</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gac5ee964eee9c88fa28d32ce3ea6478f2">DMA_HISR_DMEIF5</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gac5ee964eee9c88fa28d32ce3ea6478f2">DMA_HISR_DMEIF5</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02395" name="l02395"></a><span class="lineno"> 2395</span>}</div>
<div class="line"><a id="l02396" name="l02396"></a><span class="lineno"> 2396</span></div>
<div class="line"><a id="l02403" name="l02403"></a><span class="lineno"> 2403</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02404" name="l02404"></a><span class="lineno"> 2404</span>{</div>
<div class="line"><a id="l02405" name="l02405"></a><span class="lineno"> 2405</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab7b58e7ba316d3fc296f4433b3e62c38">DMA_HISR_DMEIF6</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab7b58e7ba316d3fc296f4433b3e62c38">DMA_HISR_DMEIF6</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02406" name="l02406"></a><span class="lineno"> 2406</span>}</div>
<div class="line"><a id="l02407" name="l02407"></a><span class="lineno"> 2407</span></div>
<div class="line"><a id="l02414" name="l02414"></a><span class="lineno"> 2414</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02415" name="l02415"></a><span class="lineno"> 2415</span>{</div>
<div class="line"><a id="l02416" name="l02416"></a><span class="lineno"> 2416</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga3bb23848f8a022a47ab4abd5aa9b7d39">DMA_HISR_DMEIF7</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga3bb23848f8a022a47ab4abd5aa9b7d39">DMA_HISR_DMEIF7</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02417" name="l02417"></a><span class="lineno"> 2417</span>}</div>
<div class="line"><a id="l02418" name="l02418"></a><span class="lineno"> 2418</span></div>
<div class="line"><a id="l02425" name="l02425"></a><span class="lineno"> 2425</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02426" name="l02426"></a><span class="lineno"> 2426</span>{</div>
<div class="line"><a id="l02427" name="l02427"></a><span class="lineno"> 2427</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga79bcc3f8e773206a66aba95c6f889d6f">DMA_LISR_FEIF0</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga79bcc3f8e773206a66aba95c6f889d6f">DMA_LISR_FEIF0</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02428" name="l02428"></a><span class="lineno"> 2428</span>}</div>
<div class="line"><a id="l02429" name="l02429"></a><span class="lineno"> 2429</span></div>
<div class="line"><a id="l02436" name="l02436"></a><span class="lineno"> 2436</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02437" name="l02437"></a><span class="lineno"> 2437</span>{</div>
<div class="line"><a id="l02438" name="l02438"></a><span class="lineno"> 2438</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gafbc4fecde60c09e12f10113a156bb922">DMA_LISR_FEIF1</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gafbc4fecde60c09e12f10113a156bb922">DMA_LISR_FEIF1</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02439" name="l02439"></a><span class="lineno"> 2439</span>}</div>
<div class="line"><a id="l02440" name="l02440"></a><span class="lineno"> 2440</span></div>
<div class="line"><a id="l02447" name="l02447"></a><span class="lineno"> 2447</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02448" name="l02448"></a><span class="lineno"> 2448</span>{</div>
<div class="line"><a id="l02449" name="l02449"></a><span class="lineno"> 2449</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga99c42b194213872753460ef9b7745213">DMA_LISR_FEIF2</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga99c42b194213872753460ef9b7745213">DMA_LISR_FEIF2</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02450" name="l02450"></a><span class="lineno"> 2450</span>}</div>
<div class="line"><a id="l02451" name="l02451"></a><span class="lineno"> 2451</span></div>
<div class="line"><a id="l02458" name="l02458"></a><span class="lineno"> 2458</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02459" name="l02459"></a><span class="lineno"> 2459</span>{</div>
<div class="line"><a id="l02460" name="l02460"></a><span class="lineno"> 2460</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">LISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5367443a1378eef82aed62ca22763952">DMA_LISR_FEIF3</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5367443a1378eef82aed62ca22763952">DMA_LISR_FEIF3</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02461" name="l02461"></a><span class="lineno"> 2461</span>}</div>
<div class="line"><a id="l02462" name="l02462"></a><span class="lineno"> 2462</span></div>
<div class="line"><a id="l02469" name="l02469"></a><span class="lineno"> 2469</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02470" name="l02470"></a><span class="lineno"> 2470</span>{</div>
<div class="line"><a id="l02471" name="l02471"></a><span class="lineno"> 2471</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacab90057201b1da9774308ff3fb6cfa1">DMA_HISR_FEIF4</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacab90057201b1da9774308ff3fb6cfa1">DMA_HISR_FEIF4</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02472" name="l02472"></a><span class="lineno"> 2472</span>}</div>
<div class="line"><a id="l02473" name="l02473"></a><span class="lineno"> 2473</span></div>
<div class="line"><a id="l02480" name="l02480"></a><span class="lineno"> 2480</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02481" name="l02481"></a><span class="lineno"> 2481</span>{</div>
<div class="line"><a id="l02482" name="l02482"></a><span class="lineno"> 2482</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0d62494b31bb830433ddd683f4872519">DMA_HISR_FEIF5</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0d62494b31bb830433ddd683f4872519">DMA_HISR_FEIF5</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02483" name="l02483"></a><span class="lineno"> 2483</span>}</div>
<div class="line"><a id="l02484" name="l02484"></a><span class="lineno"> 2484</span></div>
<div class="line"><a id="l02491" name="l02491"></a><span class="lineno"> 2491</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02492" name="l02492"></a><span class="lineno"> 2492</span>{</div>
<div class="line"><a id="l02493" name="l02493"></a><span class="lineno"> 2493</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gafb297f94bde8d1aea580683d466ca8ca">DMA_HISR_FEIF6</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gafb297f94bde8d1aea580683d466ca8ca">DMA_HISR_FEIF6</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02494" name="l02494"></a><span class="lineno"> 2494</span>}</div>
<div class="line"><a id="l02495" name="l02495"></a><span class="lineno"> 2495</span></div>
<div class="line"><a id="l02502" name="l02502"></a><span class="lineno"> 2502</span>__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02503" name="l02503"></a><span class="lineno"> 2503</span>{</div>
<div class="line"><a id="l02504" name="l02504"></a><span class="lineno"> 2504</span>  <span class="keywordflow">return</span> ((READ_BIT(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">HISR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadea53385fca360f16c4474db1cf18bc1">DMA_HISR_FEIF7</a>) == (<a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadea53385fca360f16c4474db1cf18bc1">DMA_HISR_FEIF7</a>)) ? 1UL : 0UL);</div>
<div class="line"><a id="l02505" name="l02505"></a><span class="lineno"> 2505</span>}</div>
<div class="line"><a id="l02506" name="l02506"></a><span class="lineno"> 2506</span></div>
<div class="line"><a id="l02513" name="l02513"></a><span class="lineno"> 2513</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT0(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02514" name="l02514"></a><span class="lineno"> 2514</span>{</div>
<div class="line"><a id="l02515" name="l02515"></a><span class="lineno"> 2515</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga44f83ba08feb98240a553403d977b8d1">DMA_LIFCR_CHTIF0</a>);</div>
<div class="line"><a id="l02516" name="l02516"></a><span class="lineno"> 2516</span>}</div>
<div class="line"><a id="l02517" name="l02517"></a><span class="lineno"> 2517</span></div>
<div class="line"><a id="l02524" name="l02524"></a><span class="lineno"> 2524</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT1(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02525" name="l02525"></a><span class="lineno"> 2525</span>{</div>
<div class="line"><a id="l02526" name="l02526"></a><span class="lineno"> 2526</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad2f38b0c141a9afb3943276dacdcb969">DMA_LIFCR_CHTIF1</a>);</div>
<div class="line"><a id="l02527" name="l02527"></a><span class="lineno"> 2527</span>}</div>
<div class="line"><a id="l02528" name="l02528"></a><span class="lineno"> 2528</span></div>
<div class="line"><a id="l02535" name="l02535"></a><span class="lineno"> 2535</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT2(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02536" name="l02536"></a><span class="lineno"> 2536</span>{</div>
<div class="line"><a id="l02537" name="l02537"></a><span class="lineno"> 2537</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae19254e8ad726a73c6edc01bc7cf2cfa">DMA_LIFCR_CHTIF2</a>);</div>
<div class="line"><a id="l02538" name="l02538"></a><span class="lineno"> 2538</span>}</div>
<div class="line"><a id="l02539" name="l02539"></a><span class="lineno"> 2539</span></div>
<div class="line"><a id="l02546" name="l02546"></a><span class="lineno"> 2546</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT3(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02547" name="l02547"></a><span class="lineno"> 2547</span>{</div>
<div class="line"><a id="l02548" name="l02548"></a><span class="lineno"> 2548</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0ed3ab4e5d7975f985eb25dc65f99be3">DMA_LIFCR_CHTIF3</a>);</div>
<div class="line"><a id="l02549" name="l02549"></a><span class="lineno"> 2549</span>}</div>
<div class="line"><a id="l02550" name="l02550"></a><span class="lineno"> 2550</span></div>
<div class="line"><a id="l02557" name="l02557"></a><span class="lineno"> 2557</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT4(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02558" name="l02558"></a><span class="lineno"> 2558</span>{</div>
<div class="line"><a id="l02559" name="l02559"></a><span class="lineno"> 2559</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf8f0afa9a6526f7f4413766417a56be8">DMA_HIFCR_CHTIF4</a>);</div>
<div class="line"><a id="l02560" name="l02560"></a><span class="lineno"> 2560</span>}</div>
<div class="line"><a id="l02561" name="l02561"></a><span class="lineno"> 2561</span></div>
<div class="line"><a id="l02568" name="l02568"></a><span class="lineno"> 2568</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT5(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02569" name="l02569"></a><span class="lineno"> 2569</span>{</div>
<div class="line"><a id="l02570" name="l02570"></a><span class="lineno"> 2570</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga2cef7eeccd11737c1ebf5735284046cc">DMA_HIFCR_CHTIF5</a>);</div>
<div class="line"><a id="l02571" name="l02571"></a><span class="lineno"> 2571</span>}</div>
<div class="line"><a id="l02572" name="l02572"></a><span class="lineno"> 2572</span></div>
<div class="line"><a id="l02579" name="l02579"></a><span class="lineno"> 2579</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT6(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02580" name="l02580"></a><span class="lineno"> 2580</span>{</div>
<div class="line"><a id="l02581" name="l02581"></a><span class="lineno"> 2581</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaed7cbbbc0602d00e101e3f57aa3b696a">DMA_HIFCR_CHTIF6</a>);</div>
<div class="line"><a id="l02582" name="l02582"></a><span class="lineno"> 2582</span>}</div>
<div class="line"><a id="l02583" name="l02583"></a><span class="lineno"> 2583</span></div>
<div class="line"><a id="l02590" name="l02590"></a><span class="lineno"> 2590</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_HT7(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02591" name="l02591"></a><span class="lineno"> 2591</span>{</div>
<div class="line"><a id="l02592" name="l02592"></a><span class="lineno"> 2592</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga95e9989cbd70b18d833bb4cfcb8afce9">DMA_HIFCR_CHTIF7</a>);</div>
<div class="line"><a id="l02593" name="l02593"></a><span class="lineno"> 2593</span>}</div>
<div class="line"><a id="l02594" name="l02594"></a><span class="lineno"> 2594</span></div>
<div class="line"><a id="l02601" name="l02601"></a><span class="lineno"> 2601</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC0(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02602" name="l02602"></a><span class="lineno"> 2602</span>{</div>
<div class="line"><a id="l02603" name="l02603"></a><span class="lineno"> 2603</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gab7a0b2cc41c63504195714614e59dc8e">DMA_LIFCR_CTCIF0</a>);</div>
<div class="line"><a id="l02604" name="l02604"></a><span class="lineno"> 2604</span>}</div>
<div class="line"><a id="l02605" name="l02605"></a><span class="lineno"> 2605</span></div>
<div class="line"><a id="l02612" name="l02612"></a><span class="lineno"> 2612</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC1(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02613" name="l02613"></a><span class="lineno"> 2613</span>{</div>
<div class="line"><a id="l02614" name="l02614"></a><span class="lineno"> 2614</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7494c54901b8f5bcb4894d20b8cfafed">DMA_LIFCR_CTCIF1</a>);</div>
<div class="line"><a id="l02615" name="l02615"></a><span class="lineno"> 2615</span>}</div>
<div class="line"><a id="l02616" name="l02616"></a><span class="lineno"> 2616</span></div>
<div class="line"><a id="l02623" name="l02623"></a><span class="lineno"> 2623</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC2(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02624" name="l02624"></a><span class="lineno"> 2624</span>{</div>
<div class="line"><a id="l02625" name="l02625"></a><span class="lineno"> 2625</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga52d6df2b5ab2b43da273a702fe139b59">DMA_LIFCR_CTCIF2</a>);</div>
<div class="line"><a id="l02626" name="l02626"></a><span class="lineno"> 2626</span>}</div>
<div class="line"><a id="l02627" name="l02627"></a><span class="lineno"> 2627</span></div>
<div class="line"><a id="l02634" name="l02634"></a><span class="lineno"> 2634</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC3(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02635" name="l02635"></a><span class="lineno"> 2635</span>{</div>
<div class="line"><a id="l02636" name="l02636"></a><span class="lineno"> 2636</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5210736d34dc24eb9507975921233137">DMA_LIFCR_CTCIF3</a>);</div>
<div class="line"><a id="l02637" name="l02637"></a><span class="lineno"> 2637</span>}</div>
<div class="line"><a id="l02638" name="l02638"></a><span class="lineno"> 2638</span></div>
<div class="line"><a id="l02645" name="l02645"></a><span class="lineno"> 2645</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC4(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02646" name="l02646"></a><span class="lineno"> 2646</span>{</div>
<div class="line"><a id="l02647" name="l02647"></a><span class="lineno"> 2647</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga42e529507a40f0dc4c16da7cc6d659db">DMA_HIFCR_CTCIF4</a>);</div>
<div class="line"><a id="l02648" name="l02648"></a><span class="lineno"> 2648</span>}</div>
<div class="line"><a id="l02649" name="l02649"></a><span class="lineno"> 2649</span></div>
<div class="line"><a id="l02656" name="l02656"></a><span class="lineno"> 2656</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC5(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02657" name="l02657"></a><span class="lineno"> 2657</span>{</div>
<div class="line"><a id="l02658" name="l02658"></a><span class="lineno"> 2658</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa55d19705147a6ee16effe9ec1012a72">DMA_HIFCR_CTCIF5</a>);</div>
<div class="line"><a id="l02659" name="l02659"></a><span class="lineno"> 2659</span>}</div>
<div class="line"><a id="l02660" name="l02660"></a><span class="lineno"> 2660</span></div>
<div class="line"><a id="l02667" name="l02667"></a><span class="lineno"> 2667</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC6(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02668" name="l02668"></a><span class="lineno"> 2668</span>{</div>
<div class="line"><a id="l02669" name="l02669"></a><span class="lineno"> 2669</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacd88be16962491e41e586f5109014bc6">DMA_HIFCR_CTCIF6</a>);</div>
<div class="line"><a id="l02670" name="l02670"></a><span class="lineno"> 2670</span>}</div>
<div class="line"><a id="l02671" name="l02671"></a><span class="lineno"> 2671</span></div>
<div class="line"><a id="l02678" name="l02678"></a><span class="lineno"> 2678</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TC7(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02679" name="l02679"></a><span class="lineno"> 2679</span>{</div>
<div class="line"><a id="l02680" name="l02680"></a><span class="lineno"> 2680</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadf8056629f4948fb236b4339e213cc69">DMA_HIFCR_CTCIF7</a>);</div>
<div class="line"><a id="l02681" name="l02681"></a><span class="lineno"> 2681</span>}</div>
<div class="line"><a id="l02682" name="l02682"></a><span class="lineno"> 2682</span></div>
<div class="line"><a id="l02689" name="l02689"></a><span class="lineno"> 2689</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE0(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02690" name="l02690"></a><span class="lineno"> 2690</span>{</div>
<div class="line"><a id="l02691" name="l02691"></a><span class="lineno"> 2691</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga5824a64683ce2039260c952d989bf420">DMA_LIFCR_CTEIF0</a>);</div>
<div class="line"><a id="l02692" name="l02692"></a><span class="lineno"> 2692</span>}</div>
<div class="line"><a id="l02693" name="l02693"></a><span class="lineno"> 2693</span></div>
<div class="line"><a id="l02700" name="l02700"></a><span class="lineno"> 2700</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE1(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02701" name="l02701"></a><span class="lineno"> 2701</span>{</div>
<div class="line"><a id="l02702" name="l02702"></a><span class="lineno"> 2702</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaf6d8adf52567aee2969492db65d448d4">DMA_LIFCR_CTEIF1</a>);</div>
<div class="line"><a id="l02703" name="l02703"></a><span class="lineno"> 2703</span>}</div>
<div class="line"><a id="l02704" name="l02704"></a><span class="lineno"> 2704</span></div>
<div class="line"><a id="l02711" name="l02711"></a><span class="lineno"> 2711</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE2(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02712" name="l02712"></a><span class="lineno"> 2712</span>{</div>
<div class="line"><a id="l02713" name="l02713"></a><span class="lineno"> 2713</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaa9d761752657a3d268da5434a04c6c6a">DMA_LIFCR_CTEIF2</a>);</div>
<div class="line"><a id="l02714" name="l02714"></a><span class="lineno"> 2714</span>}</div>
<div class="line"><a id="l02715" name="l02715"></a><span class="lineno"> 2715</span></div>
<div class="line"><a id="l02722" name="l02722"></a><span class="lineno"> 2722</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE3(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02723" name="l02723"></a><span class="lineno"> 2723</span>{</div>
<div class="line"><a id="l02724" name="l02724"></a><span class="lineno"> 2724</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0a51c601387d1ae49333d5ace8ae86ee">DMA_LIFCR_CTEIF3</a>);</div>
<div class="line"><a id="l02725" name="l02725"></a><span class="lineno"> 2725</span>}</div>
<div class="line"><a id="l02726" name="l02726"></a><span class="lineno"> 2726</span></div>
<div class="line"><a id="l02733" name="l02733"></a><span class="lineno"> 2733</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE4(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02734" name="l02734"></a><span class="lineno"> 2734</span>{</div>
<div class="line"><a id="l02735" name="l02735"></a><span class="lineno"> 2735</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga9e05ff4fc6bace9cc6c0f0d4ec7b3314">DMA_HIFCR_CTEIF4</a>);</div>
<div class="line"><a id="l02736" name="l02736"></a><span class="lineno"> 2736</span>}</div>
<div class="line"><a id="l02737" name="l02737"></a><span class="lineno"> 2737</span></div>
<div class="line"><a id="l02744" name="l02744"></a><span class="lineno"> 2744</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE5(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02745" name="l02745"></a><span class="lineno"> 2745</span>{</div>
<div class="line"><a id="l02746" name="l02746"></a><span class="lineno"> 2746</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga33394fe20a3567c8baaeb15ad9aab586">DMA_HIFCR_CTEIF5</a>);</div>
<div class="line"><a id="l02747" name="l02747"></a><span class="lineno"> 2747</span>}</div>
<div class="line"><a id="l02748" name="l02748"></a><span class="lineno"> 2748</span></div>
<div class="line"><a id="l02755" name="l02755"></a><span class="lineno"> 2755</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE6(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02756" name="l02756"></a><span class="lineno"> 2756</span>{</div>
<div class="line"><a id="l02757" name="l02757"></a><span class="lineno"> 2757</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga69e01e2f6a5cd1c800321e4121f8e788">DMA_HIFCR_CTEIF6</a>);</div>
<div class="line"><a id="l02758" name="l02758"></a><span class="lineno"> 2758</span>}</div>
<div class="line"><a id="l02759" name="l02759"></a><span class="lineno"> 2759</span></div>
<div class="line"><a id="l02766" name="l02766"></a><span class="lineno"> 2766</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_TE7(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02767" name="l02767"></a><span class="lineno"> 2767</span>{</div>
<div class="line"><a id="l02768" name="l02768"></a><span class="lineno"> 2768</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga84ab215e0b217547745beefb65dfefdf">DMA_HIFCR_CTEIF7</a>);</div>
<div class="line"><a id="l02769" name="l02769"></a><span class="lineno"> 2769</span>}</div>
<div class="line"><a id="l02770" name="l02770"></a><span class="lineno"> 2770</span></div>
<div class="line"><a id="l02777" name="l02777"></a><span class="lineno"> 2777</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME0(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02778" name="l02778"></a><span class="lineno"> 2778</span>{</div>
<div class="line"><a id="l02779" name="l02779"></a><span class="lineno"> 2779</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gafe80a122bf0537e8c95877ccf2b7b6d9">DMA_LIFCR_CDMEIF0</a>);</div>
<div class="line"><a id="l02780" name="l02780"></a><span class="lineno"> 2780</span>}</div>
<div class="line"><a id="l02781" name="l02781"></a><span class="lineno"> 2781</span></div>
<div class="line"><a id="l02788" name="l02788"></a><span class="lineno"> 2788</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME1(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02789" name="l02789"></a><span class="lineno"> 2789</span>{</div>
<div class="line"><a id="l02790" name="l02790"></a><span class="lineno"> 2790</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga9a5aea54a390886f7de82e87e6dfc936">DMA_LIFCR_CDMEIF1</a>);</div>
<div class="line"><a id="l02791" name="l02791"></a><span class="lineno"> 2791</span>}</div>
<div class="line"><a id="l02792" name="l02792"></a><span class="lineno"> 2792</span></div>
<div class="line"><a id="l02799" name="l02799"></a><span class="lineno"> 2799</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME2(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02800" name="l02800"></a><span class="lineno"> 2800</span>{</div>
<div class="line"><a id="l02801" name="l02801"></a><span class="lineno"> 2801</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7680fc5f5e6c0032044f1d8ab7766de8">DMA_LIFCR_CDMEIF2</a>);</div>
<div class="line"><a id="l02802" name="l02802"></a><span class="lineno"> 2802</span>}</div>
<div class="line"><a id="l02803" name="l02803"></a><span class="lineno"> 2803</span></div>
<div class="line"><a id="l02810" name="l02810"></a><span class="lineno"> 2810</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME3(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02811" name="l02811"></a><span class="lineno"> 2811</span>{</div>
<div class="line"><a id="l02812" name="l02812"></a><span class="lineno"> 2812</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gabea10cdf2d3b0773b4e6b7fc9422f361">DMA_LIFCR_CDMEIF3</a>);</div>
<div class="line"><a id="l02813" name="l02813"></a><span class="lineno"> 2813</span>}</div>
<div class="line"><a id="l02814" name="l02814"></a><span class="lineno"> 2814</span></div>
<div class="line"><a id="l02821" name="l02821"></a><span class="lineno"> 2821</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME4(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02822" name="l02822"></a><span class="lineno"> 2822</span>{</div>
<div class="line"><a id="l02823" name="l02823"></a><span class="lineno"> 2823</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga0d70d58a4423ac8973c30ddbc7404b44">DMA_HIFCR_CDMEIF4</a>);</div>
<div class="line"><a id="l02824" name="l02824"></a><span class="lineno"> 2824</span>}</div>
<div class="line"><a id="l02825" name="l02825"></a><span class="lineno"> 2825</span></div>
<div class="line"><a id="l02832" name="l02832"></a><span class="lineno"> 2832</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME5(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02833" name="l02833"></a><span class="lineno"> 2833</span>{</div>
<div class="line"><a id="l02834" name="l02834"></a><span class="lineno"> 2834</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga15b404d9e1601cf3627cbf0163b50221">DMA_HIFCR_CDMEIF5</a>);</div>
<div class="line"><a id="l02835" name="l02835"></a><span class="lineno"> 2835</span>}</div>
<div class="line"><a id="l02836" name="l02836"></a><span class="lineno"> 2836</span></div>
<div class="line"><a id="l02843" name="l02843"></a><span class="lineno"> 2843</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME6(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02844" name="l02844"></a><span class="lineno"> 2844</span>{</div>
<div class="line"><a id="l02845" name="l02845"></a><span class="lineno"> 2845</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga7f73fa93a4e01fbf279e920eca139807">DMA_HIFCR_CDMEIF6</a>);</div>
<div class="line"><a id="l02846" name="l02846"></a><span class="lineno"> 2846</span>}</div>
<div class="line"><a id="l02847" name="l02847"></a><span class="lineno"> 2847</span></div>
<div class="line"><a id="l02854" name="l02854"></a><span class="lineno"> 2854</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_DME7(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02855" name="l02855"></a><span class="lineno"> 2855</span>{</div>
<div class="line"><a id="l02856" name="l02856"></a><span class="lineno"> 2856</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad70bf852fd8c24d79fcc104c950a589f">DMA_HIFCR_CDMEIF7</a>);</div>
<div class="line"><a id="l02857" name="l02857"></a><span class="lineno"> 2857</span>}</div>
<div class="line"><a id="l02858" name="l02858"></a><span class="lineno"> 2858</span></div>
<div class="line"><a id="l02865" name="l02865"></a><span class="lineno"> 2865</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE0(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02866" name="l02866"></a><span class="lineno"> 2866</span>{</div>
<div class="line"><a id="l02867" name="l02867"></a><span class="lineno"> 2867</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gadf6b8892189f3779f7fecf529ed87c74">DMA_LIFCR_CFEIF0</a>);</div>
<div class="line"><a id="l02868" name="l02868"></a><span class="lineno"> 2868</span>}</div>
<div class="line"><a id="l02869" name="l02869"></a><span class="lineno"> 2869</span></div>
<div class="line"><a id="l02876" name="l02876"></a><span class="lineno"> 2876</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE1(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02877" name="l02877"></a><span class="lineno"> 2877</span>{</div>
<div class="line"><a id="l02878" name="l02878"></a><span class="lineno"> 2878</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga96cea0049553ab806bbc956f52528c37">DMA_LIFCR_CFEIF1</a>);</div>
<div class="line"><a id="l02879" name="l02879"></a><span class="lineno"> 2879</span>}</div>
<div class="line"><a id="l02880" name="l02880"></a><span class="lineno"> 2880</span></div>
<div class="line"><a id="l02887" name="l02887"></a><span class="lineno"> 2887</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE2(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02888" name="l02888"></a><span class="lineno"> 2888</span>{</div>
<div class="line"><a id="l02889" name="l02889"></a><span class="lineno"> 2889</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gae0f58173c721a4cee3f3885b352fa2a3">DMA_LIFCR_CFEIF2</a>);</div>
<div class="line"><a id="l02890" name="l02890"></a><span class="lineno"> 2890</span>}</div>
<div class="line"><a id="l02891" name="l02891"></a><span class="lineno"> 2891</span></div>
<div class="line"><a id="l02898" name="l02898"></a><span class="lineno"> 2898</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE3(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02899" name="l02899"></a><span class="lineno"> 2899</span>{</div>
<div class="line"><a id="l02900" name="l02900"></a><span class="lineno"> 2900</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">LIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gad9432964145dc55af9186aea425e9963">DMA_LIFCR_CFEIF3</a>);</div>
<div class="line"><a id="l02901" name="l02901"></a><span class="lineno"> 2901</span>}</div>
<div class="line"><a id="l02902" name="l02902"></a><span class="lineno"> 2902</span></div>
<div class="line"><a id="l02909" name="l02909"></a><span class="lineno"> 2909</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE4(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02910" name="l02910"></a><span class="lineno"> 2910</span>{</div>
<div class="line"><a id="l02911" name="l02911"></a><span class="lineno"> 2911</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga1e5ea118900178d4fa2d19656c1b48ff">DMA_HIFCR_CFEIF4</a>);</div>
<div class="line"><a id="l02912" name="l02912"></a><span class="lineno"> 2912</span>}</div>
<div class="line"><a id="l02913" name="l02913"></a><span class="lineno"> 2913</span></div>
<div class="line"><a id="l02920" name="l02920"></a><span class="lineno"> 2920</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE5(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02921" name="l02921"></a><span class="lineno"> 2921</span>{</div>
<div class="line"><a id="l02922" name="l02922"></a><span class="lineno"> 2922</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga9a4e90af967fa0a76c842384264e0e52">DMA_HIFCR_CFEIF5</a>);</div>
<div class="line"><a id="l02923" name="l02923"></a><span class="lineno"> 2923</span>}</div>
<div class="line"><a id="l02924" name="l02924"></a><span class="lineno"> 2924</span></div>
<div class="line"><a id="l02931" name="l02931"></a><span class="lineno"> 2931</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE6(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02932" name="l02932"></a><span class="lineno"> 2932</span>{</div>
<div class="line"><a id="l02933" name="l02933"></a><span class="lineno"> 2933</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga39a0a7f42498f71dedae8140483b7ced">DMA_HIFCR_CFEIF6</a>);</div>
<div class="line"><a id="l02934" name="l02934"></a><span class="lineno"> 2934</span>}</div>
<div class="line"><a id="l02935" name="l02935"></a><span class="lineno"> 2935</span></div>
<div class="line"><a id="l02942" name="l02942"></a><span class="lineno"> 2942</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_ClearFlag_FE7(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx)</div>
<div class="line"><a id="l02943" name="l02943"></a><span class="lineno"> 2943</span>{</div>
<div class="line"><a id="l02944" name="l02944"></a><span class="lineno"> 2944</span>  WRITE_REG(DMAx-&gt;<a class="code hl_variable" href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">HIFCR</a>, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga50332abe2e7b5a4f9cffd65d9a29382a">DMA_HIFCR_CFEIF7</a>);</div>
<div class="line"><a id="l02945" name="l02945"></a><span class="lineno"> 2945</span>}</div>
<div class="line"><a id="l02946" name="l02946"></a><span class="lineno"> 2946</span></div>
<div class="line"><a id="l02950" name="l02950"></a><span class="lineno"> 2950</span></div>
<div class="line"><a id="l02954" name="l02954"></a><span class="lineno"> 2954</span></div>
<div class="line"><a id="l02970" name="l02970"></a><span class="lineno"> 2970</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableIT_HT(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l02971" name="l02971"></a><span class="lineno"> 2971</span>{</div>
<div class="line"><a id="l02972" name="l02972"></a><span class="lineno"> 2972</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l02973" name="l02973"></a><span class="lineno"> 2973</span> </div>
<div class="line"><a id="l02974" name="l02974"></a><span class="lineno"> 2974</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20">DMA_SxCR_HTIE</a>);</div>
<div class="line"><a id="l02975" name="l02975"></a><span class="lineno"> 2975</span>}</div>
<div class="line"><a id="l02976" name="l02976"></a><span class="lineno"> 2976</span></div>
<div class="line"><a id="l02992" name="l02992"></a><span class="lineno"> 2992</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableIT_TE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l02993" name="l02993"></a><span class="lineno"> 2993</span>{</div>
<div class="line"><a id="l02994" name="l02994"></a><span class="lineno"> 2994</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l02995" name="l02995"></a><span class="lineno"> 2995</span> </div>
<div class="line"><a id="l02996" name="l02996"></a><span class="lineno"> 2996</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602">DMA_SxCR_TEIE</a>);</div>
<div class="line"><a id="l02997" name="l02997"></a><span class="lineno"> 2997</span>}</div>
<div class="line"><a id="l02998" name="l02998"></a><span class="lineno"> 2998</span></div>
<div class="line"><a id="l03014" name="l03014"></a><span class="lineno"> 3014</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableIT_TC(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03015" name="l03015"></a><span class="lineno"> 3015</span>{</div>
<div class="line"><a id="l03016" name="l03016"></a><span class="lineno"> 3016</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03017" name="l03017"></a><span class="lineno"> 3017</span> </div>
<div class="line"><a id="l03018" name="l03018"></a><span class="lineno"> 3018</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7">DMA_SxCR_TCIE</a>);</div>
<div class="line"><a id="l03019" name="l03019"></a><span class="lineno"> 3019</span>}</div>
<div class="line"><a id="l03020" name="l03020"></a><span class="lineno"> 3020</span></div>
<div class="line"><a id="l03036" name="l03036"></a><span class="lineno"> 3036</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableIT_DME(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03037" name="l03037"></a><span class="lineno"> 3037</span>{</div>
<div class="line"><a id="l03038" name="l03038"></a><span class="lineno"> 3038</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03039" name="l03039"></a><span class="lineno"> 3039</span> </div>
<div class="line"><a id="l03040" name="l03040"></a><span class="lineno"> 3040</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41">DMA_SxCR_DMEIE</a>);</div>
<div class="line"><a id="l03041" name="l03041"></a><span class="lineno"> 3041</span>}</div>
<div class="line"><a id="l03042" name="l03042"></a><span class="lineno"> 3042</span></div>
<div class="line"><a id="l03058" name="l03058"></a><span class="lineno"> 3058</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_EnableIT_FE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03059" name="l03059"></a><span class="lineno"> 3059</span>{</div>
<div class="line"><a id="l03060" name="l03060"></a><span class="lineno"> 3060</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03061" name="l03061"></a><span class="lineno"> 3061</span> </div>
<div class="line"><a id="l03062" name="l03062"></a><span class="lineno"> 3062</span>  SET_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1">DMA_SxFCR_FEIE</a>);</div>
<div class="line"><a id="l03063" name="l03063"></a><span class="lineno"> 3063</span>}</div>
<div class="line"><a id="l03064" name="l03064"></a><span class="lineno"> 3064</span></div>
<div class="line"><a id="l03080" name="l03080"></a><span class="lineno"> 3080</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableIT_HT(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03081" name="l03081"></a><span class="lineno"> 3081</span>{</div>
<div class="line"><a id="l03082" name="l03082"></a><span class="lineno"> 3082</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03083" name="l03083"></a><span class="lineno"> 3083</span> </div>
<div class="line"><a id="l03084" name="l03084"></a><span class="lineno"> 3084</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20">DMA_SxCR_HTIE</a>);</div>
<div class="line"><a id="l03085" name="l03085"></a><span class="lineno"> 3085</span>}</div>
<div class="line"><a id="l03086" name="l03086"></a><span class="lineno"> 3086</span></div>
<div class="line"><a id="l03102" name="l03102"></a><span class="lineno"> 3102</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableIT_TE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03103" name="l03103"></a><span class="lineno"> 3103</span>{</div>
<div class="line"><a id="l03104" name="l03104"></a><span class="lineno"> 3104</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03105" name="l03105"></a><span class="lineno"> 3105</span> </div>
<div class="line"><a id="l03106" name="l03106"></a><span class="lineno"> 3106</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602">DMA_SxCR_TEIE</a>);</div>
<div class="line"><a id="l03107" name="l03107"></a><span class="lineno"> 3107</span>}</div>
<div class="line"><a id="l03108" name="l03108"></a><span class="lineno"> 3108</span></div>
<div class="line"><a id="l03124" name="l03124"></a><span class="lineno"> 3124</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableIT_TC(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03125" name="l03125"></a><span class="lineno"> 3125</span>{</div>
<div class="line"><a id="l03126" name="l03126"></a><span class="lineno"> 3126</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03127" name="l03127"></a><span class="lineno"> 3127</span> </div>
<div class="line"><a id="l03128" name="l03128"></a><span class="lineno"> 3128</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7">DMA_SxCR_TCIE</a>);</div>
<div class="line"><a id="l03129" name="l03129"></a><span class="lineno"> 3129</span>}</div>
<div class="line"><a id="l03130" name="l03130"></a><span class="lineno"> 3130</span></div>
<div class="line"><a id="l03146" name="l03146"></a><span class="lineno"> 3146</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableIT_DME(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03147" name="l03147"></a><span class="lineno"> 3147</span>{</div>
<div class="line"><a id="l03148" name="l03148"></a><span class="lineno"> 3148</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03149" name="l03149"></a><span class="lineno"> 3149</span> </div>
<div class="line"><a id="l03150" name="l03150"></a><span class="lineno"> 3150</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41">DMA_SxCR_DMEIE</a>);</div>
<div class="line"><a id="l03151" name="l03151"></a><span class="lineno"> 3151</span>}</div>
<div class="line"><a id="l03152" name="l03152"></a><span class="lineno"> 3152</span></div>
<div class="line"><a id="l03168" name="l03168"></a><span class="lineno"> 3168</span>__STATIC_INLINE <span class="keywordtype">void</span> LL_DMA_DisableIT_FE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03169" name="l03169"></a><span class="lineno"> 3169</span>{</div>
<div class="line"><a id="l03170" name="l03170"></a><span class="lineno"> 3170</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03171" name="l03171"></a><span class="lineno"> 3171</span> </div>
<div class="line"><a id="l03172" name="l03172"></a><span class="lineno"> 3172</span>  CLEAR_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1">DMA_SxFCR_FEIE</a>);</div>
<div class="line"><a id="l03173" name="l03173"></a><span class="lineno"> 3173</span>}</div>
<div class="line"><a id="l03174" name="l03174"></a><span class="lineno"> 3174</span></div>
<div class="line"><a id="l03190" name="l03190"></a><span class="lineno"> 3190</span>__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03191" name="l03191"></a><span class="lineno"> 3191</span>{</div>
<div class="line"><a id="l03192" name="l03192"></a><span class="lineno"> 3192</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03193" name="l03193"></a><span class="lineno"> 3193</span> </div>
<div class="line"><a id="l03194" name="l03194"></a><span class="lineno"> 3194</span>  <span class="keywordflow">return</span> ((READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20">DMA_SxCR_HTIE</a>) == <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20">DMA_SxCR_HTIE</a>) ? 1UL : 0UL);</div>
<div class="line"><a id="l03195" name="l03195"></a><span class="lineno"> 3195</span>}</div>
<div class="line"><a id="l03196" name="l03196"></a><span class="lineno"> 3196</span></div>
<div class="line"><a id="l03212" name="l03212"></a><span class="lineno"> 3212</span>__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03213" name="l03213"></a><span class="lineno"> 3213</span>{</div>
<div class="line"><a id="l03214" name="l03214"></a><span class="lineno"> 3214</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03215" name="l03215"></a><span class="lineno"> 3215</span> </div>
<div class="line"><a id="l03216" name="l03216"></a><span class="lineno"> 3216</span>  <span class="keywordflow">return</span> ((READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602">DMA_SxCR_TEIE</a>) == <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602">DMA_SxCR_TEIE</a>) ? 1UL : 0UL);</div>
<div class="line"><a id="l03217" name="l03217"></a><span class="lineno"> 3217</span>}</div>
<div class="line"><a id="l03218" name="l03218"></a><span class="lineno"> 3218</span></div>
<div class="line"><a id="l03234" name="l03234"></a><span class="lineno"> 3234</span>__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03235" name="l03235"></a><span class="lineno"> 3235</span>{</div>
<div class="line"><a id="l03236" name="l03236"></a><span class="lineno"> 3236</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03237" name="l03237"></a><span class="lineno"> 3237</span> </div>
<div class="line"><a id="l03238" name="l03238"></a><span class="lineno"> 3238</span>  <span class="keywordflow">return</span> ((READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7">DMA_SxCR_TCIE</a>) == <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7">DMA_SxCR_TCIE</a>) ? 1UL : 0UL);</div>
<div class="line"><a id="l03239" name="l03239"></a><span class="lineno"> 3239</span>}</div>
<div class="line"><a id="l03240" name="l03240"></a><span class="lineno"> 3240</span></div>
<div class="line"><a id="l03256" name="l03256"></a><span class="lineno"> 3256</span>__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03257" name="l03257"></a><span class="lineno"> 3257</span>{</div>
<div class="line"><a id="l03258" name="l03258"></a><span class="lineno"> 3258</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03259" name="l03259"></a><span class="lineno"> 3259</span> </div>
<div class="line"><a id="l03260" name="l03260"></a><span class="lineno"> 3260</span>  <span class="keywordflow">return</span> ((READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;CR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41">DMA_SxCR_DMEIE</a>) == <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41">DMA_SxCR_DMEIE</a>) ? 1UL : 0UL);</div>
<div class="line"><a id="l03261" name="l03261"></a><span class="lineno"> 3261</span>}</div>
<div class="line"><a id="l03262" name="l03262"></a><span class="lineno"> 3262</span></div>
<div class="line"><a id="l03278" name="l03278"></a><span class="lineno"> 3278</span>__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(<span class="keyword">const</span> <a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream)</div>
<div class="line"><a id="l03279" name="l03279"></a><span class="lineno"> 3279</span>{</div>
<div class="line"><a id="l03280" name="l03280"></a><span class="lineno"> 3280</span>  uint32_t dma_base_addr = (uint32_t)DMAx;</div>
<div class="line"><a id="l03281" name="l03281"></a><span class="lineno"> 3281</span> </div>
<div class="line"><a id="l03282" name="l03282"></a><span class="lineno"> 3282</span>  <span class="keywordflow">return</span> ((READ_BIT(((<a class="code hl_struct" href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a> *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))-&gt;FCR, <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1">DMA_SxFCR_FEIE</a>) == <a class="code hl_define" href="group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1">DMA_SxFCR_FEIE</a>) ? 1UL : 0UL);</div>
<div class="line"><a id="l03283" name="l03283"></a><span class="lineno"> 3283</span>}</div>
<div class="line"><a id="l03284" name="l03284"></a><span class="lineno"> 3284</span></div>
<div class="line"><a id="l03288" name="l03288"></a><span class="lineno"> 3288</span> </div>
<div class="line"><a id="l03289" name="l03289"></a><span class="lineno"> 3289</span><span class="preprocessor">#if defined(USE_FULL_LL_DRIVER)</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03293" name="l03293"></a><span class="lineno"> 3293</span> </div>
<div class="line"><a id="l03294" name="l03294"></a><span class="lineno"> 3294</span>uint32_t LL_DMA_Init(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);</div>
<div class="line"><a id="l03295" name="l03295"></a><span class="lineno"> 3295</span>uint32_t LL_DMA_DeInit(<a class="code hl_struct" href="struct_d_m_a___type_def.html">DMA_TypeDef</a> *DMAx, uint32_t Stream);</div>
<div class="line"><a id="l03296" name="l03296"></a><span class="lineno"> 3296</span><span class="keywordtype">void</span> LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);</div>
<div class="line"><a id="l03297" name="l03297"></a><span class="lineno"> 3297</span></div>
<div class="line"><a id="l03301" name="l03301"></a><span class="lineno"> 3301</span><span class="preprocessor">#endif </span><span class="comment">/* USE_FULL_LL_DRIVER */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03302" name="l03302"></a><span class="lineno"> 3302</span></div>
<div class="line"><a id="l03306" name="l03306"></a><span class="lineno"> 3306</span></div>
<div class="line"><a id="l03310" name="l03310"></a><span class="lineno"> 3310</span> </div>
<div class="line"><a id="l03311" name="l03311"></a><span class="lineno"> 3311</span><span class="preprocessor">#endif </span><span class="comment">/* DMA1 || DMA2 */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03312" name="l03312"></a><span class="lineno"> 3312</span></div>
<div class="line"><a id="l03316" name="l03316"></a><span class="lineno"> 3316</span> </div>
<div class="line"><a id="l03317" name="l03317"></a><span class="lineno"> 3317</span><span class="preprocessor">#ifdef __cplusplus</span></div>
<div class="line"><a id="l03318" name="l03318"></a><span class="lineno"> 3318</span>}</div>
<div class="line"><a id="l03319" name="l03319"></a><span class="lineno"> 3319</span><span class="preprocessor">#endif</span></div>
<div class="line"><a id="l03320" name="l03320"></a><span class="lineno"> 3320</span> </div>
<div class="line"><a id="l03321" name="l03321"></a><span class="lineno"> 3321</span><span class="preprocessor">#endif </span><span class="comment">/* __STM32H7xx_LL_DMA_H */</span><span class="preprocessor"></span></div>
<div class="line"><a id="l03322" name="l03322"></a><span class="lineno"> 3322</span> </div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga01fd1397b41221f5bdf6f107cb92e196"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga01fd1397b41221f5bdf6f107cb92e196">DMA_LISR_DMEIF3</a></div><div class="ttdeci">#define DMA_LISR_DMEIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8899</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga04304a9f8891e325247c0aaa4c9fac72"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga04304a9f8891e325247c0aaa4c9fac72">DMA_LISR_HTIF1</a></div><div class="ttdeci">#define DMA_LISR_HTIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8923</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0a51c601387d1ae49333d5ace8ae86ee"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0a51c601387d1ae49333d5ace8ae86ee">DMA_LIFCR_CTEIF3</a></div><div class="ttdeci">#define DMA_LIFCR_CTEIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9020</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0cd826db0b9ea5544d1a93beb90f8972"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0cd826db0b9ea5544d1a93beb90f8972">DMA_LISR_TEIF1</a></div><div class="ttdeci">#define DMA_LISR_TEIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8926</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0d39c14138e9ff216c203b288137144b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0d39c14138e9ff216c203b288137144b">DMA_HISR_HTIF6</a></div><div class="ttdeci">#define DMA_HISR_HTIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8970</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0d62494b31bb830433ddd683f4872519"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0d62494b31bb830433ddd683f4872519">DMA_HISR_FEIF5</a></div><div class="ttdeci">#define DMA_HISR_FEIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8994</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0d70d58a4423ac8973c30ddbc7404b44"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0d70d58a4423ac8973c30ddbc7404b44">DMA_HIFCR_CDMEIF4</a></div><div class="ttdeci">#define DMA_HIFCR_CDMEIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9130</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga0ed3ab4e5d7975f985eb25dc65f99be3"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga0ed3ab4e5d7975f985eb25dc65f99be3">DMA_LIFCR_CHTIF3</a></div><div class="ttdeci">#define DMA_LIFCR_CHTIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9017</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga11f412d256043bec3e01ceef7f2099f2"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga11f412d256043bec3e01ceef7f2099f2">DMA_SxCR_PFCTRL</a></div><div class="ttdeci">#define DMA_SxCR_PFCTRL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8830</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga13a7fe097608bc5031d42ba69effed20"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga13a7fe097608bc5031d42ba69effed20">DMA_SxCR_HTIE</a></div><div class="ttdeci">#define DMA_SxCR_HTIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8836</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga14c115d71a4e3b3c4da360108288154c"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga14c115d71a4e3b3c4da360108288154c">DMA_SxCR_PL</a></div><div class="ttdeci">#define DMA_SxCR_PL</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8798</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga15b404d9e1601cf3627cbf0163b50221"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga15b404d9e1601cf3627cbf0163b50221">DMA_HIFCR_CDMEIF5</a></div><div class="ttdeci">#define DMA_HIFCR_CDMEIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9115</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga16bc78076551c42cbdc084e9d0006bd4"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga16bc78076551c42cbdc084e9d0006bd4">DMA_SxCR_DIR</a></div><div class="ttdeci">#define DMA_SxCR_DIR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8825</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga1a7ec01955fb504a5aa4f9f16a9ac52c"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga1a7ec01955fb504a5aa4f9f16a9ac52c">DMA_HISR_TEIF6</a></div><div class="ttdeci">#define DMA_HISR_TEIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8973</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga1e5ea118900178d4fa2d19656c1b48ff"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga1e5ea118900178d4fa2d19656c1b48ff">DMA_HIFCR_CFEIF4</a></div><div class="ttdeci">#define DMA_HIFCR_CFEIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9133</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga29c5d5c559dd14646fdc170e74f1f03b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga29c5d5c559dd14646fdc170e74f1f03b">DMA_SxCR_PINC</a></div><div class="ttdeci">#define DMA_SxCR_PINC</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8819</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga2cef7eeccd11737c1ebf5735284046cc"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga2cef7eeccd11737c1ebf5735284046cc">DMA_HIFCR_CHTIF5</a></div><div class="ttdeci">#define DMA_HIFCR_CHTIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9109</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga33394fe20a3567c8baaeb15ad9aab586"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga33394fe20a3567c8baaeb15ad9aab586">DMA_HIFCR_CTEIF5</a></div><div class="ttdeci">#define DMA_HIFCR_CTEIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9112</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga39a0a7f42498f71dedae8140483b7ced"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga39a0a7f42498f71dedae8140483b7ced">DMA_HIFCR_CFEIF6</a></div><div class="ttdeci">#define DMA_HIFCR_CFEIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9103</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga3bb23848f8a022a47ab4abd5aa9b7d39"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga3bb23848f8a022a47ab4abd5aa9b7d39">DMA_HISR_DMEIF7</a></div><div class="ttdeci">#define DMA_HISR_DMEIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8961</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga40a8216c2ca395553c72b00d087087c6"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga40a8216c2ca395553c72b00d087087c6">DMA_SxCR_TRBUFF</a></div><div class="ttdeci">#define DMA_SxCR_TRBUFF</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8789</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga429e04913f0ea2ec973e5e82c0264766"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga429e04913f0ea2ec973e5e82c0264766">DMAMUX_CxCR_DMAREQ_ID</a></div><div class="ttdeci">#define DMAMUX_CxCR_DMAREQ_ID</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9158</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga42e529507a40f0dc4c16da7cc6d659db"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga42e529507a40f0dc4c16da7cc6d659db">DMA_HIFCR_CTCIF4</a></div><div class="ttdeci">#define DMA_HIFCR_CTCIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9121</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga44c16978164026a81f5b07280e800e7f"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga44c16978164026a81f5b07280e800e7f">DMA_SxFCR_FTH</a></div><div class="ttdeci">#define DMA_SxFCR_FTH</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8883</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga44e5bf8adbb2646d325cba8d5dd670d8"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga44e5bf8adbb2646d325cba8d5dd670d8">DMA_LISR_TCIF3</a></div><div class="ttdeci">#define DMA_LISR_TCIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8890</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga44f83ba08feb98240a553403d977b8d1"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga44f83ba08feb98240a553403d977b8d1">DMA_LIFCR_CHTIF0</a></div><div class="ttdeci">#define DMA_LIFCR_CHTIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9062</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga502380abb155eb3b37a2ca9359e2da2e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga502380abb155eb3b37a2ca9359e2da2e">DMA_SxCR_PBURST</a></div><div class="ttdeci">#define DMA_SxCR_PBURST</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8784</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga50332abe2e7b5a4f9cffd65d9a29382a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga50332abe2e7b5a4f9cffd65d9a29382a">DMA_HIFCR_CFEIF7</a></div><div class="ttdeci">#define DMA_HIFCR_CFEIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9088</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5210736d34dc24eb9507975921233137"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5210736d34dc24eb9507975921233137">DMA_LIFCR_CTCIF3</a></div><div class="ttdeci">#define DMA_LIFCR_CTCIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9014</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga52d6df2b5ab2b43da273a702fe139b59"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga52d6df2b5ab2b43da273a702fe139b59">DMA_LIFCR_CTCIF2</a></div><div class="ttdeci">#define DMA_LIFCR_CTCIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9029</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5367443a1378eef82aed62ca22763952"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5367443a1378eef82aed62ca22763952">DMA_LISR_FEIF3</a></div><div class="ttdeci">#define DMA_LISR_FEIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8902</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga53a1cde736b2afc5a394a67849f0c497"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga53a1cde736b2afc5a394a67849f0c497">DMA_SxCR_DBM</a></div><div class="ttdeci">#define DMA_SxCR_DBM</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8795</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga56094479dc9b173b00ccfb199d8a2853"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga56094479dc9b173b00ccfb199d8a2853">DMA_SxFCR_FS</a></div><div class="ttdeci">#define DMA_SxFCR_FS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8874</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5824a64683ce2039260c952d989bf420"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5824a64683ce2039260c952d989bf420">DMA_LIFCR_CTEIF0</a></div><div class="ttdeci">#define DMA_LIFCR_CTEIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9065</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5c1174bff38faf5d87b71521bce8f84f"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5c1174bff38faf5d87b71521bce8f84f">DMA_SxCR_MBURST</a></div><div class="ttdeci">#define DMA_SxCR_MBURST</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8779</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga5dfaba3a5db7cdcbddf9ee5974b44c2f"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga5dfaba3a5db7cdcbddf9ee5974b44c2f">DMA_LISR_TEIF3</a></div><div class="ttdeci">#define DMA_LISR_TEIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8896</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6181727d13abbc46283ff22ce359e3b9"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6181727d13abbc46283ff22ce359e3b9">DMA_LISR_HTIF0</a></div><div class="ttdeci">#define DMA_LISR_HTIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8938</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga62e0e1a1121885de705e618855ba83b0"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga62e0e1a1121885de705e618855ba83b0">DMA_SxNDT</a></div><div class="ttdeci">#define DMA_SxNDT</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8850</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga64f15eaf1dd30450d1d35ee517507321"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga64f15eaf1dd30450d1d35ee517507321">DMA_HISR_TCIF5</a></div><div class="ttdeci">#define DMA_HISR_TCIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8982</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga69e01e2f6a5cd1c800321e4121f8e788"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga69e01e2f6a5cd1c800321e4121f8e788">DMA_HIFCR_CTEIF6</a></div><div class="ttdeci">#define DMA_HIFCR_CTEIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9097</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6ae47cc2cd2e985d29cb6b0bb65da1d7"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6ae47cc2cd2e985d29cb6b0bb65da1d7">DMA_SxCR_TCIE</a></div><div class="ttdeci">#define DMA_SxCR_TCIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8833</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga6ca25185d14a1f0c208ec8ceadc787a6"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga6ca25185d14a1f0c208ec8ceadc787a6">DMA_LISR_HTIF2</a></div><div class="ttdeci">#define DMA_LISR_HTIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8908</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga72de97ebc9d063dceb38bada91c44878"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga72de97ebc9d063dceb38bada91c44878">DMA_LISR_DMEIF0</a></div><div class="ttdeci">#define DMA_LISR_DMEIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8944</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7494c54901b8f5bcb4894d20b8cfafed"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7494c54901b8f5bcb4894d20b8cfafed">DMA_LIFCR_CTCIF1</a></div><div class="ttdeci">#define DMA_LIFCR_CTCIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9044</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga74d540802cadde42bdd6debae5d8ab89"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga74d540802cadde42bdd6debae5d8ab89">DMA_LISR_TEIF2</a></div><div class="ttdeci">#define DMA_LISR_TEIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8911</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7680fc5f5e6c0032044f1d8ab7766de8"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7680fc5f5e6c0032044f1d8ab7766de8">DMA_LIFCR_CDMEIF2</a></div><div class="ttdeci">#define DMA_LIFCR_CDMEIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9038</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga771a295832a584a3777ede523a691719"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga771a295832a584a3777ede523a691719">DMA_SxCR_MINC</a></div><div class="ttdeci">#define DMA_SxCR_MINC</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8816</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga79bcc3f8e773206a66aba95c6f889d6f"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga79bcc3f8e773206a66aba95c6f889d6f">DMA_LISR_FEIF0</a></div><div class="ttdeci">#define DMA_LISR_FEIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8947</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga7f73fa93a4e01fbf279e920eca139807"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga7f73fa93a4e01fbf279e920eca139807">DMA_HIFCR_CDMEIF6</a></div><div class="ttdeci">#define DMA_HIFCR_CDMEIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9100</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga84ab215e0b217547745beefb65dfefdf"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga84ab215e0b217547745beefb65dfefdf">DMA_HIFCR_CTEIF7</a></div><div class="ttdeci">#define DMA_HIFCR_CTEIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9082</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga8617bf8160d1027879ffd354e04908d9"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga8617bf8160d1027879ffd354e04908d9">DMA_HISR_HTIF5</a></div><div class="ttdeci">#define DMA_HISR_HTIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8985</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga89406bb954742665691c0ac2f8d95ec9"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga89406bb954742665691c0ac2f8d95ec9">DMA_SxFCR_DMDIS</a></div><div class="ttdeci">#define DMA_SxFCR_DMDIS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8880</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga9005d4b958193fbd701c879eede467c1"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga9005d4b958193fbd701c879eede467c1">DMA_HISR_TEIF4</a></div><div class="ttdeci">#define DMA_HISR_TEIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9003</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga95e9989cbd70b18d833bb4cfcb8afce9"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga95e9989cbd70b18d833bb4cfcb8afce9">DMA_HIFCR_CHTIF7</a></div><div class="ttdeci">#define DMA_HIFCR_CHTIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9079</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga960f094539b5afc7f9d5e45b7909afe6"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga960f094539b5afc7f9d5e45b7909afe6">DMA_HISR_TEIF7</a></div><div class="ttdeci">#define DMA_HISR_TEIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8958</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga96cea0049553ab806bbc956f52528c37"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga96cea0049553ab806bbc956f52528c37">DMA_LIFCR_CFEIF1</a></div><div class="ttdeci">#define DMA_LIFCR_CFEIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9056</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga99c42b194213872753460ef9b7745213"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga99c42b194213872753460ef9b7745213">DMA_LISR_FEIF2</a></div><div class="ttdeci">#define DMA_LISR_FEIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8917</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga9a4e90af967fa0a76c842384264e0e52"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga9a4e90af967fa0a76c842384264e0e52">DMA_HIFCR_CFEIF5</a></div><div class="ttdeci">#define DMA_HIFCR_CFEIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9118</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga9a5aea54a390886f7de82e87e6dfc936"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga9a5aea54a390886f7de82e87e6dfc936">DMA_LIFCR_CDMEIF1</a></div><div class="ttdeci">#define DMA_LIFCR_CDMEIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9053</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_ga9e05ff4fc6bace9cc6c0f0d4ec7b3314"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#ga9e05ff4fc6bace9cc6c0f0d4ec7b3314">DMA_HIFCR_CTEIF4</a></div><div class="ttdeci">#define DMA_HIFCR_CTEIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9127</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaa10c891ee2ec333b7f87eea5886d574f"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaa10c891ee2ec333b7f87eea5886d574f">DMA_LISR_HTIF3</a></div><div class="ttdeci">#define DMA_LISR_HTIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8893</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaa4903814bfc12dd6193416374fbddf8c"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaa4903814bfc12dd6193416374fbddf8c">DMA_LISR_DMEIF1</a></div><div class="ttdeci">#define DMA_LISR_DMEIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8929</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaa55d19705147a6ee16effe9ec1012a72"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaa55d19705147a6ee16effe9ec1012a72">DMA_HIFCR_CTCIF5</a></div><div class="ttdeci">#define DMA_HIFCR_CTCIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9106</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaa9d761752657a3d268da5434a04c6c6a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaa9d761752657a3d268da5434a04c6c6a">DMA_LIFCR_CTEIF2</a></div><div class="ttdeci">#define DMA_LIFCR_CTEIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9035</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaabf69fe92e9a44167535365b0fe4ea9e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaabf69fe92e9a44167535365b0fe4ea9e">DMA_SxCR_EN</a></div><div class="ttdeci">#define DMA_SxCR_EN</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8845</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab7a0b2cc41c63504195714614e59dc8e"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab7a0b2cc41c63504195714614e59dc8e">DMA_LIFCR_CTCIF0</a></div><div class="ttdeci">#define DMA_LIFCR_CTCIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9059</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gab7b58e7ba316d3fc296f4433b3e62c38"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gab7b58e7ba316d3fc296f4433b3e62c38">DMA_HISR_DMEIF6</a></div><div class="ttdeci">#define DMA_HISR_DMEIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8976</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaba9ca2264bc381abe0f4183729ab1fb1"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaba9ca2264bc381abe0f4183729ab1fb1">DMA_SxFCR_FEIE</a></div><div class="ttdeci">#define DMA_SxFCR_FEIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8871</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gabc7edcd7404f0dcf19a724dfad22026a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gabc7edcd7404f0dcf19a724dfad22026a">DMA_LISR_DMEIF2</a></div><div class="ttdeci">#define DMA_LISR_DMEIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8914</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gabea10cdf2d3b0773b4e6b7fc9422f361"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gabea10cdf2d3b0773b4e6b7fc9422f361">DMA_LIFCR_CDMEIF3</a></div><div class="ttdeci">#define DMA_LIFCR_CDMEIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9023</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gac5ee964eee9c88fa28d32ce3ea6478f2"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gac5ee964eee9c88fa28d32ce3ea6478f2">DMA_HISR_DMEIF5</a></div><div class="ttdeci">#define DMA_HISR_DMEIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8991</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gacab90057201b1da9774308ff3fb6cfa1"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gacab90057201b1da9774308ff3fb6cfa1">DMA_HISR_FEIF4</a></div><div class="ttdeci">#define DMA_HISR_FEIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9009</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gacaecc56f94a9af756d077cf7df1b6c41"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gacaecc56f94a9af756d077cf7df1b6c41">DMA_SxCR_DMEIE</a></div><div class="ttdeci">#define DMA_SxCR_DMEIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8842</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gacd88be16962491e41e586f5109014bc6"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gacd88be16962491e41e586f5109014bc6">DMA_HIFCR_CTCIF6</a></div><div class="ttdeci">#define DMA_HIFCR_CTCIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9091</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad20a0a5e103def436d4e329fc0888482"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad20a0a5e103def436d4e329fc0888482">DMA_HISR_TCIF7</a></div><div class="ttdeci">#define DMA_HISR_TCIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8952</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad29468aa609150e241d9ae62c477cf45"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad29468aa609150e241d9ae62c477cf45">DMA_HISR_TCIF6</a></div><div class="ttdeci">#define DMA_HISR_TCIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8967</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad2f38b0c141a9afb3943276dacdcb969"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad2f38b0c141a9afb3943276dacdcb969">DMA_LIFCR_CHTIF1</a></div><div class="ttdeci">#define DMA_LIFCR_CHTIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9047</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad43cdafa5acfcd683b7a2ee8976dd8ba"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad43cdafa5acfcd683b7a2ee8976dd8ba">DMA_LISR_TEIF0</a></div><div class="ttdeci">#define DMA_LISR_TEIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8941</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad70bf852fd8c24d79fcc104c950a589f"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad70bf852fd8c24d79fcc104c950a589f">DMA_HIFCR_CDMEIF7</a></div><div class="ttdeci">#define DMA_HIFCR_CDMEIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9085</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gad9432964145dc55af9186aea425e9963"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gad9432964145dc55af9186aea425e9963">DMA_LIFCR_CFEIF3</a></div><div class="ttdeci">#define DMA_LIFCR_CFEIF3</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9026</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadba8d24329c676d70560eda0b8c1e5b0"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadba8d24329c676d70560eda0b8c1e5b0">DMA_HISR_HTIF4</a></div><div class="ttdeci">#define DMA_HISR_HTIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9000</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadbc3f7e52c0688bed4b71fa37666901d"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadbc3f7e52c0688bed4b71fa37666901d">DMA_LISR_TCIF0</a></div><div class="ttdeci">#define DMA_LISR_TCIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8935</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadc248dbc519cc580621cdadcdd8741fb"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadc248dbc519cc580621cdadcdd8741fb">DMA_SxCR_CIRC</a></div><div class="ttdeci">#define DMA_SxCR_CIRC</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8822</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadd36c677ee53f56dc408cd549e64cf7d"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadd36c677ee53f56dc408cd549e64cf7d">DMA_SxCR_CT</a></div><div class="ttdeci">#define DMA_SxCR_CT</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8792</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadea53385fca360f16c4474db1cf18bc1"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadea53385fca360f16c4474db1cf18bc1">DMA_HISR_FEIF7</a></div><div class="ttdeci">#define DMA_HISR_FEIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8964</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadf6b8892189f3779f7fecf529ed87c74"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadf6b8892189f3779f7fecf529ed87c74">DMA_LIFCR_CFEIF0</a></div><div class="ttdeci">#define DMA_LIFCR_CFEIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9071</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gadf8056629f4948fb236b4339e213cc69"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gadf8056629f4948fb236b4339e213cc69">DMA_HIFCR_CTCIF7</a></div><div class="ttdeci">#define DMA_HIFCR_CTCIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9076</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae02aec39ded937b3ce816d3df4520d9b"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae02aec39ded937b3ce816d3df4520d9b">DMA_LISR_TCIF1</a></div><div class="ttdeci">#define DMA_LISR_TCIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8920</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae057bfb6e5d7b553b668a050fcdb152d"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae057bfb6e5d7b553b668a050fcdb152d">DMA_SxM1AR_M1A</a></div><div class="ttdeci">#define DMA_SxM1AR_M1A</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9148</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae0f58173c721a4cee3f3885b352fa2a3"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae0f58173c721a4cee3f3885b352fa2a3">DMA_LIFCR_CFEIF2</a></div><div class="ttdeci">#define DMA_LIFCR_CFEIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9041</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae19254e8ad726a73c6edc01bc7cf2cfa"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae19254e8ad726a73c6edc01bc7cf2cfa">DMA_LIFCR_CHTIF2</a></div><div class="ttdeci">#define DMA_LIFCR_CHTIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9032</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gae9a98cb706a722d726d8ec6e9fe4a773"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gae9a98cb706a722d726d8ec6e9fe4a773">DMA_SxCR_MSIZE</a></div><div class="ttdeci">#define DMA_SxCR_MSIZE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8806</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaeb929908d2e7fdef2136c20c93377c70"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaeb929908d2e7fdef2136c20c93377c70">DMA_SxCR_PINCOS</a></div><div class="ttdeci">#define DMA_SxCR_PINCOS</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8803</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaed7cbbbc0602d00e101e3f57aa3b696a"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaed7cbbbc0602d00e101e3f57aa3b696a">DMA_HIFCR_CHTIF6</a></div><div class="ttdeci">#define DMA_HIFCR_CHTIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9094</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaeee99c36ba3ea56cdb4f73a0b01fb602"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaeee99c36ba3ea56cdb4f73a0b01fb602">DMA_SxCR_TEIE</a></div><div class="ttdeci">#define DMA_SxCR_TEIE</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8839</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf16fb0e5d87f704c89824f961bfb7637"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf16fb0e5d87f704c89824f961bfb7637">DMA_HISR_TEIF5</a></div><div class="ttdeci">#define DMA_HISR_TEIF5</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8988</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf21350cce8c4cb5d7c6fcf5edc930cf8"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf21350cce8c4cb5d7c6fcf5edc930cf8">DMA_LISR_TCIF2</a></div><div class="ttdeci">#define DMA_LISR_TCIF2</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8905</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf535d1a3209d2e2e0e616e2d7501525d"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf535d1a3209d2e2e0e616e2d7501525d">DMA_HISR_HTIF7</a></div><div class="ttdeci">#define DMA_HISR_HTIF7</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8955</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf6d8adf52567aee2969492db65d448d4"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf6d8adf52567aee2969492db65d448d4">DMA_LIFCR_CTEIF1</a></div><div class="ttdeci">#define DMA_LIFCR_CTEIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9050</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf716f1bc12ea70f49802d84fb77646e8"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf716f1bc12ea70f49802d84fb77646e8">DMA_HISR_DMEIF4</a></div><div class="ttdeci">#define DMA_HISR_DMEIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9006</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gaf8f0afa9a6526f7f4413766417a56be8"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gaf8f0afa9a6526f7f4413766417a56be8">DMA_HIFCR_CHTIF4</a></div><div class="ttdeci">#define DMA_HIFCR_CHTIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9124</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gafb297f94bde8d1aea580683d466ca8ca"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gafb297f94bde8d1aea580683d466ca8ca">DMA_HISR_FEIF6</a></div><div class="ttdeci">#define DMA_HISR_FEIF6</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8979</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gafbc4fecde60c09e12f10113a156bb922"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gafbc4fecde60c09e12f10113a156bb922">DMA_LISR_FEIF1</a></div><div class="ttdeci">#define DMA_LISR_FEIF1</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8932</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gafcce25c245499f9e62cb757e1871d973"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gafcce25c245499f9e62cb757e1871d973">DMA_HISR_TCIF4</a></div><div class="ttdeci">#define DMA_HISR_TCIF4</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:8997</div></div>
<div class="ttc" id="agroup___peripheral___registers___bits___definition_html_gafe80a122bf0537e8c95877ccf2b7b6d9"><div class="ttname"><a href="group___peripheral___registers___bits___definition.html#gafe80a122bf0537e8c95877ccf2b7b6d9">DMA_LIFCR_CDMEIF0</a></div><div class="ttdeci">#define DMA_LIFCR_CDMEIF0</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:9068</div></div>
<div class="ttc" id="astm32h7xx_8h_html"><div class="ttname"><a href="stm32h7xx_8h.html">stm32h7xx.h</a></div><div class="ttdoc">CMSIS STM32H7xx Device Peripheral Access Layer Header File.</div></div>
<div class="ttc" id="astm32h7xx__ll__dmamux_8h_html"><div class="ttname"><a href="stm32h7xx__ll__dmamux_8h.html">stm32h7xx_ll_dmamux.h</a></div><div class="ttdoc">Header file of DMAMUX LL module.</div></div>
<div class="ttc" id="astruct_d_m_a___stream___type_def_html"><div class="ttname"><a href="struct_d_m_a___stream___type_def.html">DMA_Stream_TypeDef</a></div><div class="ttdoc">DMA Controller.</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:601</div></div>
<div class="ttc" id="astruct_d_m_a___type_def_html"><div class="ttname"><a href="struct_d_m_a___type_def.html">DMA_TypeDef</a></div><div class="ttdef"><b>Definition</b> stm32h723xx.h:611</div></div>
<div class="ttc" id="astruct_d_m_a___type_def_html_a01a90a5fcd6459e10b81c0ab737dd2e3"><div class="ttname"><a href="struct_d_m_a___type_def.html#a01a90a5fcd6459e10b81c0ab737dd2e3">DMA_TypeDef::HISR</a></div><div class="ttdeci">__IO uint32_t HISR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:613</div></div>
<div class="ttc" id="astruct_d_m_a___type_def_html_a11adb689c874d38b49fa44990323b653"><div class="ttname"><a href="struct_d_m_a___type_def.html#a11adb689c874d38b49fa44990323b653">DMA_TypeDef::LIFCR</a></div><div class="ttdeci">__IO uint32_t LIFCR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:614</div></div>
<div class="ttc" id="astruct_d_m_a___type_def_html_a1e4f50b935bab2520788ae936f2e55c1"><div class="ttname"><a href="struct_d_m_a___type_def.html#a1e4f50b935bab2520788ae936f2e55c1">DMA_TypeDef::HIFCR</a></div><div class="ttdeci">__IO uint32_t HIFCR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:615</div></div>
<div class="ttc" id="astruct_d_m_a___type_def_html_aacb4a0977d281bc809cb5974e178bc2b"><div class="ttname"><a href="struct_d_m_a___type_def.html#aacb4a0977d281bc809cb5974e178bc2b">DMA_TypeDef::LISR</a></div><div class="ttdeci">__IO uint32_t LISR</div><div class="ttdef"><b>Definition</b> stm32h723xx.h:612</div></div>
<div class="ttc" id="astruct_d_m_a_m_u_x___channel___type_def_html"><div class="ttname"><a href="struct_d_m_a_m_u_x___channel___type_def.html">DMAMUX_Channel_TypeDef</a></div><div class="ttdef"><b>Definition</b> stm32h723xx.h:634</div></div>
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